ADL5519ACPZ-R7 datasheet(22/40 Pages) AD

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ADL5519

Rev. 0 | Page 22 of 40

TEMPERATURE SENSOR INTERFACE

The ADL5519 provides a temperature sensor output capable of

driving 4 mA. The temperature scaling factor of the output voltage

is ~4.48 mV/°C. The typical absolute voltage at 27°C is approxi-

mately 1.36 V.

TEMP

VPSR

INTERNAL

VPTAT

12kΩ

4kΩ

COMR

Figure 54. TEMP Interface Simplified Schematic

VREF INTERFACE

The VREF pin provides a highly stable voltage reference. The

voltage on the VREF pin is 1.15 V, which is capable of driving

3 mA. An equivalent internal resistance is connected from

VREF to COMR for 3 mA sink capability.

POWER-DOWN INTERFACE

The operating and stand-by currents for the ADL5519 at 27°C

are approximately 60 mA and less than 1 mA, respectively. To

completely power down the ADL5519, the PWDN and ADJA,

ADJB pins must be pulled within 200 mV of the supply voltage.

When powered on, the output reaches to within 0.1 dB of its

steady-state value in about 0.5 μs; the reference voltage is avail-

able to full accuracy in a much shorter time.

This wake-up response time varies, depending on the input

coupling network and the capacitance at the CLPA, CLPB pins.

PWDN disables the OUTP, OUTN, VREF, and TEMP pins. The

power-down pin, PWDN, is a high impedance pin.

The ADJA and ADJB pins, when pulled within 200 mV of the

supply voltage, disable OUTA and OUTB, respectively.

SETPOINT INTERFACE—VSTA, VSTB

The VSTA, VSTB inputs are high impedance (40 kΩ) pins that

drive inputs of internal op amps. The VSET voltage appears across

the internal 1.5 kΩ resistor to generate a current, ISET. When a

portion of VOUT is applied to VSTA, VSTB, the feedback loop forces

−ID × log10(VIN/VINTERCEPT) = ISET

(2)

If VSET = VOUT/2x, then ISET = VOUT/(2x × 1.5 kΩ).

The result is

VOUT = (−ID × 1.5 kΩ × 2x) × log10(VIN/VINTERCEPT)

ISET

VSET

1.5kΩ

20kΩ

COMM

Figure 55. VSTA, VSTB Interface Simplified Schematic

The slope is given by −ID × 2x × 1.5 kΩ = −22 mV/dB × x. For

example, if a resistor divider to ground is used to generate a VSET

voltage of VOUT/2, then x = 2. The slope is set to −880 V/decade

or −44 mV/dB. See the Altering the Slope section for additional

information.

OUTPUT INTERFACE—OUTA, OUTB

The OUTA, OUTB pins are driven by a push-pull output stage.

The rise time of the output is limited mainly by the slew on CLPA,

CLPB. The fall time is an RC-limited slew given by the load capaci-

tance and the pull-down resistance at OUTA, OUTB. There is

an internal pull-down resistor of 1.6 kΩ The resistive load at

OUTA, OUTB can be placed in parallel with the internal pull-

down resistor to reduce the discharge time. OUTA, OUTB can

source greater than 10 mA.

OUTA,

OUTB

VPSA, VPSB

CLPA,

CLPB

1.2kΩ

400Ω

COMR

Figure 56. OUTA, OUTB Interface Simplified Schematic

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