Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

Operating Input Voltage

(*) Note 1

6

26

V

Output Voltage

°C

4.8

4.9

5.2

5.1

V

V

Line Regulation

5

25

mV

SVR

Supply Voltage Rejection

µF

55

dB

Load Regulation

15

50

mV

Dropout Voltage

0.45

0.70

V

0.90

V

Quiescent Current

7

25

12

70

mA

mA

Short Circuit Current

1.8

A

Rset Output Saturation Voltage

0.40

0.40

V

V

Power On-Off Reset out Peak

Voltage

1K

0.65

1.0

V

Reset Output Leakage Current

(high level)

50

µA

Reset Pulse Delay Time

20

ms

°C

–40

4.75

4.70

V

V

Delay Capacitor Charging

Current (current generator)

20

µA

Transition

+ 0.03V

0.04V

V

Delay Comparator Threshold

Reset out = ”1” H to L Transition

3.2

3.8

V

Reset out = ”0” L to H Transition

3.7

4

4.4

V

Delay Comparator Hysteresis

500

mV

EXTERNAL COMPENSATION

Since the purpose of a voltageregulatoris to supply

a fixed output voltage in spite of supply and load

variations, the open loop gain of the regulator must

be very high at low frequencies.This may cause in-

stability as a result of the various poles present in

the loop. To avoid this instability dominant pole

compensationis used to reduce phase shiftsdue to

other poles at the unity gain frequency. The lower

the frequencyof theseother poles, the greater must

be the capacitor used to create the dominant pole

for the same DC gain.

Where the output transistor is a lateral PNP type

there is a pole in the regulation loop at a frequency

too low to be compensated by a capacitor wich can

be integrated. An external compensation is there-

fore necessary so a very high value capacitor must

be connected from the output to ground.

The parassitic equivalentseries resistanceof theca-

pacitor used adds a zero to the regulation loop. This

zero may compromise the stability of the system

since its effect tends to cancel the effect of the pole

added. In regulators this ESR must be less than 3

Ω

and the minimum capacitor value is 47

µF.

L4922

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