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SSM2603CPZ-R2 数据表(PDF) 5 Page - Analog Devices |
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SSM2603CPZ-R2 数据表(HTML) 5 Page - Analog Devices |
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5 / 32 page  SSM2603 Rev. 0 | Page 5 of 32 TIMING CHARACTERISTICS Table 3. I2C® Timing Limit Parameter tMIN tMAX Unit Description tSCS 600 ns Start condition setup time tSCH 600 ns Start condition hold time tPH 600 ns SCLK pulse width high tPL 1.3 μs SCLK pulse width low fSCLK 0 526 kHz SCLK frequency tDS 100 ns Data setup time tDH 900 ns Data hold time tRT 300 ns SDIN and SCLK rise time tFT 300 ns SDIN and SCLK fall time tHCS 600 ns Stop condition setup time SCLK SDIN tRT tSCH tPL tDS tPH tDH tFT tSCS tHCS Figure 2. I2C Timing Table 4. Digital Audio Interface Slave Mode Timing Limit Parameter tMIN tMAX Unit Description tDS 10 ns PBDAT setup time from BCLK rising edge tDH 10 ns PBDAT hold time from BCLK rising edge tLRSU 10 ns RECLRC/PBLRC setup time to BCLK rising edge tLRH 10 ns RECLRC/PBLRC hold time to BCLK rising edge tDD 30 ns RECDAT propagation delay from BCLK falling edge (external load of 70 pF) tBCH 25 ns BCLK pulse width high tBCL 25 ns BCLK pulse width low tBCY 50 ns BCLK cycle time BCLK PBLRC/ RECLRC PBDAT RECDAT tBCL tDS tLRSU tLRH tBCH tBCY tDD tDH Figure 3. Digital Audio Interface Slave Mode Timing |
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