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ADE7169 数据表(PDF) 55 Page - Analog Devices |
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ADE7169 数据表(HTML) 55 Page - Analog Devices |
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55 / 144 page ![]() ADE7566/ADE7569/ADE7166/ADE7169 Rev. A | Page 55 of 144 PHASE COMPENSATION RMS CALCULATION The ADE7566/ADE7569/ADE7166/ADE7169 must work with transducers that can have inherent phase errors. For example, a phase error of 0.1° to 0.3° is not uncommon for a current transformer (CT). These phase errors can vary from part to part, and they must be corrected to perform accurate power calculations. The errors associated with phase mismatch are particularly noticeable at low power factors. The ADE7566/ ADE7569/ADE7166/ADE7169 provide a means of digitally calibrating these small phase errors. The part allows a small time delay or time advance to be introduced into the signal processing chain to compensate for small phase errors. Because the compensation is in time, this technique should only be used for small phase errors in the range of 0.1° to 0.5°. Correcting large phase errors using a time shift technique can introduce significant phase errors at higher harmonics. The root mean square (rms) value of a continuous signal V(t) is defined as ∫ × = T rms dt t V T V 0 2 ) ( 1 (3) For time sampling signals, rms calculation involves squaring the signal, taking the average, and obtaining the square root. The ADE7566/ADE7569/ADE7166/ADE7169 implement this method by serially squaring the input, averaging them, and then taking the square root of the average. The averaging part of this signal processing is done by implementing a low-pass filter (LPF3 in Figure 59, Figure 61, and Figure 62). This LPF has a −3 dB cut-off frequency of 2 Hz when MCLK = 4.096 MHz. () ) sin( 2 t V t V ω × = (4) The phase calibration register (PHCAL[7:0]) is a twos complement, signed, single-byte register that has values ranging from 0x82 (−126d) to 0x68 (+104d). where V is the rms voltage. ( t V V t V ω − = 2 cos ) ( 2 2 2 ) (5) The PHCAL register is centered at 0x40, meaning that writing 0x40 to the register gives 0 delay. By changing this register, the time delay in the voltage channel signal path can change from −231.93 μs to +48.83 μs (MCLK = 4.096 MHz). One LSB is equivalent to 1.22 μs (4.096 MHz/5) time delay or advance. A line frequency of 60 Hz gives a phase resolution of 0.026° at the fundamental (that is, 360° × 1.22 μs × 60 Hz). When this signal goes through LPF3, the cos(2ωt) term is attenu- ated and only the dc term Vrms2 goes through (see Figure 59). V LPF3 INPUT V 2 (t) = V2 – V2 cos(2ωt) V 2 (t) = V2 V (t) = √2 × V sin(ωt) Figure 58 illustrates how the phase compensation is used to remove a 0.1° phase lead in the current channel due to the external transducer. To cancel the lead (0.1°) in the current channel, a phase lead must also be introduced into the voltage channel. The resolution of the phase adjustment allows the introduction of a phase lead in increments of 0.026°. The phase lead is achieved by introducing a time advance into the voltage channel. A time advance of 4.88 μs is made by writing −4 (0x3C) to the time delay block, thus reducing the amount of time delay by 4.88 μs, or equivalently, a phase lead of approximately 0.1° at a line frequency of 60 Hz (0x3C represents −4 because the register is centered with 0 at 0x40). Figure 59. RMS Signal Processing The Irms signal can be read from the waveform register by setting the WAVMODE register (0x0D) and setting the WFSM bit in the Interrupt Enable 3 SFR (MIRQENH, 0xDB). Like the current and voltage channels waveform sampling modes, the waveform data is available at sample rates of 25.6 kSPS, 12.8 kSPS, 6.4 kSPS, or 3.2 kSPS. It is important to note that when the current input is larger than 40% of full scale, the Irms waveform sample register does not represent the true processed rms value. The rms value processed with this level of input is larger than the 24-bit read by the wave- form register, making the value read truncated on the high end. 1 1 0 1 0 0 1 70 PGA1 IPA IN I ADC 1 HPF 24 PGA2 VP VN V ADC 2 24 LPF2 V I 60Hz 0.1° I V CHANNEL 2 DELAY REDUCED BY 4.48µs (0.1°LEAD AT 60Hz) 0x0B IN PHCAL[7:0] PHCAL[7:0] –231.93µs TO +48.83µs 60Hz 1 1 DELAY BLOCK 1.22µs/LSB Figure 58. Phase Calibration |
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