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ADE7169 数据表(PDF) 13 Page - Analog Devices |
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ADE7169 数据表(HTML) 13 Page - Analog Devices |
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13 / 144 page  ADE7566/ADE7569/ADE7166/ADE7169 Rev. A | Page 13 of 144 Table 9. SPI Slave Mode Timing (SPICPHA = 1) Parameters Parameter Description Min Typ Max Unit tSS SS 145 ns to SCLK edge tSL SCLK low pulse width 6 × tCORE1 ns tSH SCLK high pulse width 6 × tCORE1 ns tDAV Data output valid after SCLK edge 25 ns tDSU Data input setup time before SCLK edge 0 ns tDHD Data input hold time after SCLK edge 2 × tCORE1 + 0.5 μs μs tDF Data output fall time 19 ns tDR Data output rise time 19 ns tSR SCLK rise time 19 ns tSF SCLK fall time 19 ns tSFS SS 0 ns high after SCLK edge 1 tCORE depends on the clock divider or CD bits of the POWCON SFR (see Table 25); tCORE = 2CD/4.096 MHz. MSB MOSI BITS [6:1] tDHD tDSU MSB IN LSB IN BITS [6:1] LSB tDR tDF tDAV MISO tSL tSH tSR tSF tSFS tSS SCLK (SPICPOL = 1) SCLK (SPICPOL = 0) SS Figure 7. SPI Slave Mode Timing (SPICPHA = 1) |
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