Pulse-skipping operation is enabled by default in order to maximize efficiency also in low load current

range. The transition between PWM and pulse-skipping occurs approximately below 1A, however there

is a region in which the two operation modes coexist rather than a definite boundary. That can be seen

on the scope as an irregularity of the waveforms but does not have much influence both on output ripple

and efficiency.

Those who do not appreciate asynchronous operation of the pulse-skipping mode can disable it for both

regulators, by setting switch 2 on 1. That maintains PWM operation up to very low output currents where,

however, the regulation becomes incompatible with the switching frequency. This means that the mini-

mum ON-time of the high-side MOSFET is too long for the thruput energy level at the operating fre-

quency. Thus the control system begins skipping conduction cycles to avoid the output voltage drifting

upwards.

Table 1 shows the complete L4992 EVAL KIT parts list. Critical components characteristics are given in

detail.

DEMO BOARD EVALUATION

The following diagrams and tables show the typical performance of the demonstration board in terms of

efficiency, line regulation and load regulation. The 12V linear regulator and REG5 are also characterized.

Table 2: PWM Regulators: Optimum Efficiency

Parameter

Test Condition

Value

Unit

+3.3V Maximum Efficiency

RUN3 = RUN5 = HIGH, NOSKIP = LOW

95.2

94.6

%

+5.1V Maximum Efficiency

RUN3 = LOW, NOSKIP = LOW

96.4

95.8

%

DESIGN PROCEDURE (continued)

Table 3: PWM regulators: Line and Load Regulation.

Parameter

Test Condition

Value

Unit

+3.3V Line Regulation

RUN5 = LOW, NOSKIP = LOW, 6 < Vin < 20V

2

15

mV

+5.1V Line Regulation

RUN3 = LOW, NOSKIP = LOW, 6 < Vin < 20V

3

20

mV

+3.3V Load Regulation

RUN5 = LOW, NOSKIP = LOW, 5 mA < Iout < 3A

85

70

mV

+5.1V Load Regulation

RUN3 = LOW, NOSKIP = LOW, 5 mA < Iout < 3A

90

75

mV

L4992

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