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L4992 数据表(PDF) 6 Page - STMicroelectronics |
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L4992 数据表(HTML) 6 Page - STMicroelectronics |
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6 / 26 page ![]() DETAILED FUNCTIONAL DESCRIPTION In the L4992 block diagram six fundamental functional blocks can be identified: 3.3V step-down PWM switching regulator (pins 17 to 20, 24 to 27). 5.1V step-down PWM switching regulator (pins 1, 4 to 8, 30 to 32). 12V low drop-out linear regulator (pins 21,22). 5V low drop-out linear regulator (pin 3). 3.3V reference voltage generator (pin 12). Power Management section (pins 9 to 11, 14,16). The chip is supplied through pin VIN (2), typically by a battery pack or the output of an AC-DC adapter, with a voltage that can range from 5.5 to 25V. The return of the bias current of the device is the signal ground pin SGND (13), which references the internal logic circuitry. The drivers of the external MOSFET’s have their separate current return for each section, namely the power ground pins PGND3 (28) and PGND5 (29). Take care of keeping separate the routes of signal ground and the two power ground pins when laying out the PCB (see "Layout and grounding" section). The two PWM regulators share the internal oscillator, programmable or synchronizable through pin OSC (15). +3.3V AND +5.1V PWM REGULATORS Each PWM regulator includes control circuitry as well as gate-drive circuits for a step-down DC-DC con- verter in buck topology using synchronous rectification and current mode control. The two regulators are independent and almost identical. As one can see in the Block Diagram, they share only the oscillator and the internal supply and differ for the pre-set output voltages and for the con- trol circuit that links the +3.3V section to the operation of the 12V linear regulator (see the relevant sec- tion). Each converter can be turned on and off independently: RUN3 and RUN5 are control inputs which dis- able the relevant section when a low logic level (below 0.8 V) is applied and enable its operation with a high logic level (above 2.4 V). When both inputs are low the device is in stand-by condition and its cur- rent consumption is extremely reduced (less than 120 µA over the entire input voltage range). Oscillator The oscillator, which does not require any external timing component, controls the PWM switching fre- quency. This can be either 200 or 300 kHz, depending on the logic state of the control pin OSC, or else can be synchronized by an external oscillator. If OSC is grounded or connected to pin REG5 (5V) the oscillator works at 200kHz. By connecting OSC to a 2.5 V voltage, 300 kHz operation will be selected. Instead, if pin OSC is fed with an external signal like the one shown in fig. 1, the oscillator will be synchronized by its falling edges. Considering the spread of the oscillator, synchronization can be guaranteed for frequencies above 230kHz. Even though a maximum frequency value is in practice imposed by efficiency considerations it should be noticed that increasing frequency too much arises problems (noise, subharmonic oscillation, etc.) without significant benefits in terms of external component size reduction and better dynamic per- formance. The oscillator imposes a time interval (300 ns min.), during which the high-side MOSFET is definitely OFF, to recharge the bootstrap capacitor (see "MOSFET’s Drivers" section). This, implies a limit on the maximum duty cycle (88.5% @ fsw = 300kHz, 92.6% @ fsw = 200kHz, worst case) which, in turn, im- poses a limit on the minimum operating input voltage. PWM regulation The control loop does not employ a traditional error amplifier in favour of an error summing comparator which sums the reference voltage, the feedback signal, the voltage drop across an external sense resis- tor and a slope compensation ramp (to avoid subharmonic oscillation with duty cycles greater then 50%) with the appropriate signs. The output latch of both controllers is set by every pulse coming from the oscillator. That turns off the low-side MOSFET (synchronous rectifier) and, after a short delay (typ. 75 ns) to prevent cross-conduc- tion, turns on the high-side one, thus allowing energy to be drawn from the input source and stored in the inductor. L4992 6/26 |
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