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CLC5957PCASM 数据表(PDF) 4 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部件名 CLC5957PCASM
功能描述  12-Bit, 70MSPS Broadband Monolithic A/D Converter
PDF  16 Pages
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制造商  NSC [National Semiconductor (TI)]
网页  http://www.national.com
标志 NSC - National Semiconductor (TI)

CLC5957PCASM 数据表(HTML) 4 Page - National Semiconductor (TI)

  CLC5957PCASM Datasheet HTML 1Page - National Semiconductor (TI) CLC5957PCASM Datasheet HTML 2Page - National Semiconductor (TI) CLC5957PCASM Datasheet HTML 3Page - National Semiconductor (TI) CLC5957PCASM Datasheet HTML 4Page - National Semiconductor (TI) CLC5957PCASM Datasheet HTML 5Page - National Semiconductor (TI) CLC5957PCASM Datasheet HTML 6Page - National Semiconductor (TI) CLC5957PCASM Datasheet HTML 7Page - National Semiconductor (TI) CLC5957PCASM Datasheet HTML 8Page - National Semiconductor (TI) CLC5957PCASM Datasheet HTML 9Page - National Semiconductor (TI) Next Button
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Converter Electrical Characteristics (Continued)
The following specifications apply for AV
CC =DVCC = +5V, 66MSPS. Boldface limits apply for TA =Tmin = −40˚C to Tmax =
+85˚C, all other limits T
A = 25˚C (Note 3).
Symbol
Parameter
Conditions
Min
Typ
Max
Units
ANALOG INPUTS
V
IN
Analog Diff Input Voltage Range
2.048
V
PP
R
IN (SE)
Analog Input Resistance
(Single-Ended)
500
Ω
R
IN (Diff)
Analog Input Resistance (Differential)
1000
Ω
C
IN
Analog Input Capacitance
(Single-ended)
2pF
ENCODE INPUTS (UNIVERSAL)
V
IH
Logic Input High Voltage (Note
4),(Note 5)
5V
V
IL
Logic Input Low Voltage(Note
4),(Note 5)
0V
Differential Input Swing (Note
4),(Note 5)
0.2
V
DIGITAL OUTPUTS
V
OL
Logic Output Low Voltage (Note 2)
0.01
0.4
V
V
OH
Logic Output High Voltage (Note 2)
OUTLEV = 1 (open)
3.2
3.5
3.8
V
OUTLEV = 0 (GND)
2.4
2.7
3.0
V
TIMING (Note 6)
Maximum Conversion Rate
(ENCODE) (Note 2)
70
75
MSPS
Minimum Conversion Rate
(ENCODE)
10
MSPS
t
P
Pulse Width High (ENCODE) (Note
4)
50% threshold
7.1
ns
t
M
Pulse Width Low (ENCODE) (Note 4) 50% threshold
7.1
ns
t
DNV
ENCODE falling edge to DATA not
valid (Note 4)
8.3
ns
t
DGV
ENCODE falling edge to DATA
guaranteed valid (Note 4)
17.8
ns
t
DAV
Rising ENCODE to rising DAV delay
(Note 4)
50% threshold
8.3
12.6
ns
t
S
DATA setup time before rising DAV
(Note 4)
t
M−2.4
ns
t
H
DATA hold time after rising DAV
(Note 4)
t
P−1.6
ns
Pipeline latency
3.0
clk cycle
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