Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

LIN Error Amplifier

Transconductance

0.8

mA/V

Zout

Error Amplifier Output

Impedance

2M

Ω

Logic Input Voltage BRK; INUA;

INUB; INUC; INLA; INLB; INLC

2V

0.8

V

Logic Input Current BRK; INUA;

INUB; INUC; INLA; INLB; INLC

-1

mA

-0.1

mA

Upper/Lower Turn-on Delay

Table 1

see Fig. 3

0.7

µs

0.15

µs

Upper/Lower Turn-off Delay

15

µs

0.5

µs

dV/dt

Source DMOS Slew-Rate

(PWM)

see Fig. 3

10

V/

µs

dV/dt

Source DMOS Slew-Rate (LIN)

see Fig. 3

1

V/

µs

dV/dt

Sink DMOS Output Turn-off

Slew-Rate

Note 3; R = 100K

Ω

0.15

V/

µs

Internal Clock Frequency

380

KHz

PWM Cutoff Time

R=100K

Ω; C=180pF, Note 4;

see Fig. 2

40

µs

Shutdown Temperature

160

°C

Recovery Temperature

120

°C

Notes:

3) The resistance of the RC network defines the dv/dt value.

ELECTRICAL CHARACTERISTICS (continued)

Table 1

INPUT STATE

OUTPUT STATE

INUA

INUB

INUC

INLA

INLB

INLC

A

B

C

LLL

H

H

H*

*

*

LLL

LL

L

H

H

H

HHH

L

L

L

*

*

*

HHH

HH

H

L

L

L

H = The Upper DMOS is ON

L = The Lower DMOS is ON

* = Tristate condition

L6232E

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