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25CS160T-H/MS 数据表(PDF) 13 Page - Microchip Technology |
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25CS160T-H/MS 数据表(HTML) 13 Page - Microchip Technology |
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13 / 53 page ![]() 2026 Microchip Technology Inc. and its subsidiaries Preliminary DS20007008B-page 13 25CS160 3.0 MEMORY ORGANIZATION 3.1 EEPROM Organization The 25CS160 is internally organized as 64 pages of 32 bytes each. 3.2 Device Registers The 25CS160 contains four types of registers that modulate device operation and/or report on the current status of the device. These registers are: • STATUS register • Security register • Undervoltage Lockout Detection (UVLO) register • Identification register 3.2.1 STATUS REGISTER The STATUS register is a 16-bit combination of volatile and nonvolatile bits. It is used to modify the write protection functions as well as store various aspects of the current status of the device. Details about the STATUS register are covered in Section 6.0 “STATUS Register”. 3.2.2 SECURITY REGISTER The Security register is split into a read-only section and a user-programmable, lockable ID page section. The read-only section contains a preprogrammed, globally unique, 128-bit serial number. The user-programmable (lockable ID page) section of the Security register is ideal for applications that need to irreversibly protect critical or sensitive application data from ever being altered. See Section 9.0 “Security Register” for more details about the Security register. 3.2.3 UNDERVOLTAGE LOCKOUT REGISTER The Undervoltage Lockout Detection (UVLO) register is an 8-bit nonvolatile register that can be used to modify the threshold of the undervoltage detection circuit. Information on this function can be found in Section 10.0 “Programmable UnderVoltage Lockout”. 3.2.4 IDENTIFICATION REGISTER The Identification register is a 40-bit nonvolatile, read-only register that contains device identification data in compliance with the JEDEC® standard for “Manufacturer and Device ID Read Methodology for SPI Compatible Serial Interface Memory Devices.” The contents and format of the Identification register can be reviewed in Section 11.0 “Identification Register”. FIGURE 3-1: MEMORY ORGANIZATION Memory Address Range Protection Features 16-Kbit EEPROM 512-bit Security Register 16-Kbit Address Range: 0000h – 07FFh 128-bit Serial Number Address Range (0000h – 000Fh) Legacy Write Protection • Block Protection (BP bits in STATUS register) • Hardware Protection (WP pin via STATUS register) Read-Only Permanently Lockable by Software User-Programmable, Lockable ID Page Address Range (0020h – 003Fh) Reserved for Future Use (FFh) Address Range (0010h – 001Fh) |
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