REGISTER DEFINITION and 3bit Address Code

Table 1: Status Register (A.C. 001)

Bit

Name

POR Initial

Value

7

6

5

4

3

2

1

0

NC

NC

NC

NC

REVERSE SPIN

OVER TEMP.

SPIN SENSE

OVER VEL SET

1

1

0

1

Table 2: VCM Driver Register (A.C. 010)

Bit

Name

POR Initial

Value

7

6

5

4

3

2

1

0

NC

NC

NC

UNLOAD HD

LOAD HD

ENABLE ISENSE

HIGH GAIN VCM

ENABLE VCM

0

0

0

0

0

Table 3: Spin Control Register (A.C. 011)

Bit

Name

POR Initial

Value

7

6

5

4

3

2

1

0

NC

LINEAR/PWM

INCREMENT STATE

RESET STATE

RUN/SEARCH

UNI/BI

HIGH GAIN SPIN

ENABLE Spin

0

0

0

0

0

0

0

0

Table 4: VCM D/A Register (A.C. 100)

Bit

Name

POR Initial

Value

7

6

5

4

3

2

1

0

Most Significant Bit

Least Significant Bit

0

0

0

0

0

0

0

0

Table 5: Spin D/A Register (A.C. 101)

Bit

Name

POR Initial

Value

7

6

5

4

3

2

1

0

Most Significant Bit

Least Significant Bit

0

0

0

0

0

0

0

0

Table 6: Interrupt Mask Register (A.C. 110)

Bit

Name

POR Initial

Value

7

6

5

4

3

2

1

0

NC

NC

NC

NC

NC

MASK REV Spin

MASK OVER TEMP ERROR

MASK OVER VEL ERROR

0

0

0

Table 7: Phase Delay Register (A.C. 111)

Bit

Name

POR Initial

Value

7

6

5

4

3

2

1

0

NC

NC

NC

NC

Most Significant Bit

Least Significant Bit

0

0

0

0

SYSTEM BUS DESCRIPTION

The system bus is designed as a data acknow-

ledge handshanking bus. At the beginning of the

bus cycle the address and chip select are de-

coded transparently and qualified with read or

write going low. On a read operation, data must

not be driven for 5nsec after read goes low to al-

low the bus to clear. Once data is driven, data ac-

knowledge is driven low to notify the processor

that data is on the bus and ready to be read. The

processor reads the data and responds by raising

read. This is an indication that the processor has

compleated the read and cycle is complete. Data

acknowledge and data must go to high im-

pedence within 20ns to clear the bus for the next

L6245

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