AD8061/AD8062/AD8063

Rev. E | Page 16 of 20

CAPACITIVE LOAD DRIVE

DISABLE OPERATION

The AD8061/AD8062/AD8063 family is optimized for

bandwidth and speed, not for driving capacitive loads. Output

capacitance creates a pole in the amplifier’s feedback path,

leading to excessive peaking and potential oscillation. If dealing

with load capacitance is a requirement of the application, the

two strategies to consider are as follows:

The internal circuit for the AD8063 disable function is shown

in Figure 52. When the DISABLE node is pulled below 2 V

from the positive supply, the supply current decreases from

typically 6.5 mA to under 400 μA, and the AD8063 output

enters a high impedance state. If the DISABLE node is not

connected and allowed to float, the AD8063 stays biased at

full power.

•

Use a small resistor in series with the amplifier’s output and

the load capacitance.

VCC

DISABLE

TO AMPLIFIER

BIAS

VEE

2V

•

Reduce the bandwidth of the amplifier’s feedback loop by

increasing the overall noise gain.

Figure 50 shows a unity-gain follower using the series resistor

strategy. The resistor isolates the output from the capacitance

and, more importantly, creates a zero in the feedback path that

compensates for the pole created by the output capacitance.

AD8061

Figure 52. Disable Circuit of the AD8063

Figure 34 shows the AD8063 supply current vs. DISABLE

voltage. Figure 35 plots the output seen when the AD8063 input

is driven with a 10 MHz sine wave, and DISABLE is toggled

from 0 V to 5 V, illustrating the part’s turn-on and turn-off

time. Figure 33 shows the input/output isolation response with

the AD8063 shut off.

Figure 50. Series Resistor Isolating Capacitive Load

Voltage feedback amplifiers like those in the AD8061/AD8062/

AD8063 family are able to drive more capacitive load without

excessive peaking when used in higher gain configurations

because the increased noise gain reduces the bandwidth of the

overall feedback loop. Figure 51 plots the capacitance that

produces 30% overshoot vs. noise gain for a typical amplifier.

BOARD LAYOUT CONSIDERATIONS

CLOSED-LOOP GAIN

10k

1k

10

1

2

5

100

34

Maintaining the high speed performance of the AD8061/AD8062/

AD8063 family requires the use of high speed board layout

techniques and low parasitic components.

The PCB should have a ground plane covering unused portions

of the component side of the board to provide a low impedance

path. Remove the ground plane near the package to reduce

parasitic capacitance.

Proper bypassing is critical. Use a ceramic 0.1 μF chip capacitor

to bypass both supplies. Locate the chip capacitor within 3 mm

of each power pin. Additionally, connect in parallel a 4.7 μF to

10 μF tantalum electrolytic capacitor to provide charge for fast,

large signal changes at the output.

Minimizing parasitic capacitance at the amplifier’s inverting

input pin is very important. Locate the feedback resistor close to

the inverting input pin. The value of the feedback resistor may

come into play—for instance, 1 kΩ interacting with 1 pF of

parasitic capacitance creates a pole at 159 MHz. Use stripline

design techniques for signal traces longer than 25 mm. Design

them with either 50 Ω or 75 Ω characteristic impedance and

proper termination at each end.

Figure 51. Capacitive Load vs. Closed-Loop Gain