1

MS7200L/7201AL/7202AL

MOSEL VITELIC

MS7200L/01AL/02AL Rev. 1.0 January 1995

MS7200L/7201AL/7202AL

256 x 9, 512 x 9, 1K x 9

CMOS FIFO

Features

s First-In/First-Out static RAM based dual port

memory

s Three densities in a x9 configuration

s Low power versions

s Includes empty, full, and half full status flags

s Direct replacement for industry standard

Mostek and IDT

s Ultra high-speed 30 MHz FIFOs available with

33 ns cycle times.

s Fully expandable in both depth and width

s Simultaneous and asynchronous read and write

s Auto retransmit capability

s TTL compatible interface, single 5V ± 10%

power supply

s Available in 28 pin 300 mil and 600 mil plastic

DIP, 32 Pin PLCC and 330 mil SOG

Descriptions

The MS7200L/7201AL/7202AL are dual-port

static RAM based CMOS First-In/First-Out (FIFO)

memories organized in nine-bit wide words. The

devices are configured so that data is read out in

the same sequential order that it was written in.

Additional expansion logic is provided to allow for

unlimited expansion of both word size and depth.

The dual-port RAM array is internally sequenced

by independent Read and Write pointers with no

external addressing needed. Read and write

operations are fully asynchronous and may occur

simultaneously, even with the device operating at

full speed. Status flags are provided for full, empty,

and half-full conditions to eliminate data underflow

and overflow. The x9 architecture provides an

additional bit which may be used as a parity or

control bit. In addition, the devices offer a retransmit

capability which resets the Read pointer and allows

for retransmission from the beginning of the data.

The MS7200L/7201AL/7202AL are available in a

range of frequencies from 10 to 30 MHz (33 - 100 ns

cycle times). A low power version with a 500µA

power down supply current is available. They are

manufactured on Mosel-Vitelic’s high performance

1.2µ CMOS process and operate from a single 5V

power supply.

W

WRITE

CONTROL

WRITE

POINTER

READ

POINTER

READ

CONTROL

RESET

LOGIC

FLAG

LOGIC

EXPANSION

LOGIC

THREE

STATE

BUFFERS

DATA OUTPUTS (Q0-Q8)

DATA INPUTS (Q0-Q8)

R

XI

EF

HF

FF

XO

RS

FL / RT

RAM

ARRAY

256x9

512x9

1Kx9

Block Diagram

28-PIN PDIP

Pin Configurations

32-PIN PLCC

V

D6

D7

FL / RT

EF

XO / HF

CC

Q2

Q3

Q8

GND

Q1

Q0

FF

XI

D0

D1

D2

D3

D8

300 mil

600 mil

DIP

&

330 mil

SOG

W

Q6

Q5

Q4

R

Q7

RS

D5

D4

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

D

D

XI

FF

Q

Q

Q

D6

D7

NC

FL / RT

RS

EF

XO / HF

Q7

Q6

5

8

7

8

9

10

11

14

13

29

28

27

26

25

24

23

22

21

1

0

0

1

NC

2

14

D2

32 Pin PLCC

Top View

15 16 17 18 19 20

4

3

2

1 32 31 30