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MS7201AL 数据表(PDF) 2 Page - Mosel Vitelic, Corp |
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MS7201AL 数据表(HTML) 2 Page - Mosel Vitelic, Corp |
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2 / 11 page ![]() 2 MS7200L/7201AL/7202AL MOSEL VITELIC MS7200L/01AL/02AL Rev. 1.0 January 1995 Signal Descriptions INPUTS: Data In (D0 - D8) These data inputs accept 9-bit data words for sequential storage in the FIFO during write operations. CONTROLS: Reset ( RS) The reset input is active LOW. When asserted, the device is asynchronously reset, and both the read and write internal pointers are set to the first location in the FIFO. A Reset is required after power-up before a write operation can occur. Both Read Enable ( R) and Write Enable (W) must be HIGH during Reset. Read Enable ( R) The read enable input is active LOW. As long as the Empty Flag ( EF) is not set, the read cycle is started on the falling edge of this signal. The data is accessed on a First-In/First-Out basis, independent of any write activity, and is presented on the Data Output pins (Q0 - Q8). When R goes HIGH the Data Output pins return to the high impedance state, and the read pointer is incremented. When the FIFO is empty or all of the data has been read, the Empty Flag will be set and further read operations are inhibited until a valid write operation has been performed. Write Enable ( W) The write enable input is active LOW. As long as the Full Flag ( FF) is not set, the write cycle is started on the falling edge of this signal. The data present on the Data Input pins (D0 - D8) is stored sequentially, independent of any read activity. When W goes HIGH the write cycle is terminated and the write pointer is incremented. When the maximum capacity of the FIFO has been reached the Full Flag will be set, and further write operations are inhibited until a valid read operation has been performed. Expansion In ( XI) This input pin serves two purposes. When grounded, it indicates that the device is being operated in the single device mode. In Depth Expansion mode, this pin is connected to the Expansion Out Output ( XO) of the previous device. First Load/Retransmit ( FL/RT) This is a dual-purpose input. In single device mode (when Expansion In ( XI) is grounded) this pin acts as the retransmit input. A LOW pulse on this will reset the read pointer to the first memory location of the FIFO. The write pointer is unaffected. Both the read enable ( R) and write enable (W) inputs must remain HIGH during the retransmit cycle. In Depth Expansion mode this pin acts as a first load indicator. It must be grounded on the first device in the chain to indicate which device is the first to receive data. OUTPUTS: Data Output (Q0 - Q8) A 9 bit data word from the FIFO is output on these pins during read operations. They are in the high impedance state whenever R is HIGH. Empty Flag ( EF) This output is active LOW. When all of the data has been read from the FIFO (defined as when the Read pointer is one location behind the Write pointer) this flag will be set. The Data Output pins will be forced into the high impedance state, and all further read operations will be inhibited until a valid write operation has been performed (which will reset this flag). Full Flag ( FF) This output is active LOW. To prevent data overflow, when the maximum capacity of the FIFO has been reached (defined as when the Write pointer is one location behind the Read pointer) this flag will be set. All further write operations will be inhibited until a valid read operation has been performed (which will reset this flag). Expansion Out/Half Full Flag ( XO/HF) This dual-purpose output is active LOW. In single device mode (when Expansion In ( XI) is grounded) this flag will be set at the falling edge of the next write operation after the FIFO has reached one-half of its maximum capacity. This flag will remain set as long as the difference between the read pointer and the write pointer is greater than one-half of the maximum capacity of the FIFO. In Depth Expansion mode, this output is connected to the Expansion In Input of the next device in the chain. The Expansion Out pin provides a pulse to the next device in the chain when the last memory location has been reached. |
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