OPERATIONAL AMPLIFIERS DESCRIPTION

Each driver has two output stages scaled in cur-

rent by a factor K = 10.

In voltage mode configuration the two outputs are

shorted.

In charge mode configuration OUT1 drives a ca-

pacitor Cint and is closed in feedback, while

OUTK drives the piezo, mirroring the current sup-

plied to Cint, with a current multiplied by a K fac-

tor (see Fig.1).

The supply voltage can be internally generated by

the DC-DC converter, or external, maintaining the

DC-DC converter in sleep mode (PIN15 shorted

to ground), in this case the supply voltage can be

0 to V512+4 minimum value up to 80V in single

supply or V512+4 to 40V symmetrical to ground.

The drivers have 130dB DC gain and the Band-

width is 500KHz. Stability is granted with a mini-

mum gain of 20dB, for a capacitive load in the

range 0.4nF up to 24nF.

The drivers can be supplied with HVP-HVM (dou-

ble supply mode) or with HVP-Ground (single

supply mode). In both cases they can achieve a

rail-to rail output dynamic range with a maximum

load current of

±75mA.

In double supply mode the input stage has -

5V/+5V dynamic range, while in single supply

mode it has 1.2V up to 10V input dynamic range.

A 2.5V internal reference voltage is available at

one pin (Vref) that can be used to close the feed-

back if the input signal is symmetrical around

2.5V.

In this case the output dynamic is symmetrical

around 2.5V. It is present a 2.5V down level

shifter that can be connected between the input

signal and the input of the opamp, to work inter-

nally with a signal symmetrical to ground.

DC-DC CONVERTER DESCRIPTION

The DC-DC converter inside the chip can be sup-

plied from 5V up to 12V and has two parts, one to

supply the positive and one to supply the negative

voltage.

The positive one takes the reference from the pin

DC

voltage.

If DC

verter is shut down and the high voltages have to

be supplied from external. In Sleep Mode (sleep

pin) HVM is shorted to GND. When in single sup-

ply, no load has to be connected to H-bridge output

and HVM must be connected to GND.

The topology is a standard resonant full-wave

boost one: the LC oscillation is kept running all

the time and a set of comparators is used to syn-

chronize turning on and off of the power MOS in

order to have zero current and zero voltage

switching and furthermore controlled rectification.

The step-up converter is designed to work in

”Bang-Bang” mode and in Linear mode, in this

case an AC compensation network is required

(RC-comp) to guarantee the stability in a wide op-

erative range (i.e. changing coil, load, output and

input voltage...).

In Bang-Bang mode (Bang/Lin=V512 high condi-

tion) whenever the output HVP goes down fixed

tion phase is more powerful and is used to trans-

fer energy from the power supply to the output.

In Linear mode, according to the ouput voltage,

the current loaded into the coil is changing like a

-

+

HVP

HVM

Rb

1

1

K

K

C

Qpiezo=K*[Cint*(1+Ra/Rb)+C]*Vdac

Qpiezo=Cost*Vdac

Cost=k*[Cint*(1+Ra/Rb)+C]

Vdac

D98IN970A

Ra

Cpiezo

Cint

Figure 1. Charge Mode Configuration (only a suggestion, the application is completely free

according with Electrical Characteristics).

L6270 - L6271

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