SMBus System Clock Buffer for Mobile Applications

SC660E

Rev 1.0, December 06, 2006

Page 1 of 5

2200 Laurelwood Road, Santa Clara, CA 95054

Tel:(408) 855-0555

Fax:(408) 855-0550

www.SpectraLinear.com

Features

• 10 output buffers for high clock fanout applications

• Each output can be internally disabled for EMI and power

consumption reduction.

• Separate power supply for each group of 2 clock outputs

for mixed voltage application.

• < 250ps skew between output clocks.

• 28-pin SSOP package for minimum board space

• Single output Tristate pin for testability

Product Description

The device is a high fanout system clock distributor.

Its

primary application is to create the large quantity of clocks

needed to support a wide range of clock loads that are refer-

enced to a single existing clock. Loads of up to 30 pF are

supported. Primary application of this component is where

long traces are used to transport clocks from their generating

devices to their loads. The creation of EMI and the degra-

dation of waveform rise and fall times is greatly reduced by

running a single reference clock trace to this device and then

using it to regenerate the clock that drives shorter traces by

using the SC660 to generate the clocks at the target devices

EMI is therefore minimized and board real estate is saved.

Block Diagram

Pin Configuration

VDDB

OE

SDATA

SDRAM(2:3)

SCLOCK

VDD

FIN

I2C

SDRAM(0:1)

SDRAM4

SDRAM5

SDRAM(8:9)

SDRAM(6:7)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

VDDB

SDRAM9

SDRAM8

VSS

VDDB

SDRAM7

SDRAM6

VSS

OE

VDDB

SDRAM5

VSS

VSS

SCLOCK

VDDB

SDRAM0

SDRAM1

VSS

VDDB

SDRAM2

SDRAM3

VSS

FIN

VDDB

SDRAM4

VSS

VDD

SDATA