SC660E

Rev 1.0, December 06, 2006

Page 2 of 5

Input Voltage Relative to VSS:................................VSS-0.3V

Input Voltage Relative to VDDQ or AVDD: ........... VDD+0.3V

Storage Temperature: ................................. -65 C to + 150 C

Operating Temperature:.................................... 0 C to +85 C

Maximum Power Supply: ................................................ 3.5V

This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precau-

tions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper

operation, Vin and Vout should be constrained to the range:

VSS<(Vin or Vout)<VDD

Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD).

Note:

1. The voltage on any input or I/O pin cannot exceed the power pin during the power-up. Power supply sequencing is NOT required.

Pin Description

Pin No.

Name

PWR

I/O

Type

Description

9

FIN

-

I

PAD

This pin is connected to the input reference clock. This clock

must be in the range of 10.0 to 100.0 Mhz.

2,3,6,7,11,18,22,23

,26,27

Sdram(0:9)

VddB

O

BUF1

Low skew output clocks.

20

OE

-

I

PAD

Buffer Output Enable pin. This pin is low it is used to place

all output clocks (CLK1:10) in a tri state condition. This

feature facilitates in production board level testing to be

easily implemented for the clocks that this device produces.

Has internal pull-up resistor.

14

Sdata

Vdd

I/O

PAD

Serial Data for SMBus control interface. This pin receives

data streams from the SMBus bus and outputs an

acknowledge for valid data.

15

Sclock

Vdd

I

PAD

Serial Clock for SMBus control interface.

4, 8, 12, 16, 17, 21,

25

Vss

PWR

-

Ground pins for clock output buffers. These pins must be

returned to the same potential to reduce output clock skew.

1, 5, 10, 19, 24, 28

VddB

-

PWR

-

Power for output clock buffers.

13

Vdd

-

PWR

-

Pin for device core logic.