3 STATE / PUSH-PULL INPUT

The input 3st/Pp is instead intended for a digital

incoming signal. It has an internal threshold set at

1.26V; an internal bias circuit (10

µA typical) simu-

lates a high level (three-state) if the pin is discon-

nected.

THE SWITCHING OF THE OUTPUT STAGE

The cross conduction of the two transistors of an

output stage of the L6374 would be significantly

noisy, because the transistors here can carry

peak currents in excess of 100mA, and even

more in the few nanoseconds before the current

limiting circuits are really effective.

Consequently the device has been designed so

as to avoid such cross conduction. At every

switching transition, first of all the transistor in

conduction is turned off. Then, after a safe inter-

val of around 200ns, the other transistor is turned

on.

When analyzing the switching cycle, and the as-

sociated switching times, it is useful to identify

some subsequent phases:

- delay from the input pin to the output reaction;

- off transition in the output stage;

- dead time;

- on transition in the output stage.

Figure 4 helps understand such sequence. In

Vref

Vi

Vs

Vout

Hys2

Hys2

22

D94IN073

Figure 3: Input Comparator Threshold

L6374

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