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L6610

DESCRIPTION

The L6610 is a control and housekeeping IC developed in BCD technology; it is intended for acting at the sec-

ondary side of desktop PC's or server's switching power supplies, in presence of standard voltage rails (+3.3V,

±5V, ±12V) generated by a main converter and of a supply line generated by an auxiliary converter. The typical

application circuit is showed on the front page.

The Housekeeping's main function is to control and monitor the voltages generated by both the main and the

auxiliary converter: it senses those voltages, sends feedback signals to the primary controllers for regulation

and, upon detection of an undervoltage (UV), overvoltage (OV) or overcurrent (OC) condition, reports such fault

and takes proper action to protect the system.

However, the peculiar feature of this IC is its digital programming capability that enables an accurate trimming

of the output voltage rails during production test via software, without any use of external discrete trimming com-

ponents or need for manual intervention on the PSU. It is also possible to program some of the monitoring func-

tions and select how UV and OC conditions are handled in the main converter: whether latched-mode (the

information is latched and released only by forcing the restart of the IC) or bouncing-mode (an attempt is made

to automatically restart the converter after 1 second wait).

A key feature of this IC is its contribution to a very low external component count. Besides the extensive use of

onboard programmable switches, which prevents the need for external trimming components, the IC embeds

reference voltages, error amplifiers and most of the housekeeping circuitry normally required.

PIN CONNECTION (top view)

PIN DESCRIPTION

Pin #

Name

Description

1

MFAULT

Main converter on/off control. This pin is a 10mA current sink used for driving an opto-isolator. It

is normally low when PS-ON (#15) is pulled low. If a fault is detected or PS-ON goes high, this

pin goes high too. To allow power up, the functions are digitally blanked out for a period (UVB

function) and MFAULT (#1) stays low. There is no delay for the OV protection function.

2

Binv

Inverting input to the error amplifier for the 3V3 post-regulator (either mag-amp or linear). The

non-inverting input is connected to an internal 1.25V reference that can be digitally trimmed.

3

Bout

Output of the 3V3 error amplifier. It typically drives either a PNP transistor that sets the mag-amp

core or the pass element of a linear regulator. Also node for error amplifier compensation. The

maximum positive level of this output is clamped at about 3.5V to improve response time. Large

signal slew rate is limited to reduce noise sensitivity.

MFAULT

Binv

Bout

12V

5V

3V3

-12V

VREF

PS-ON

PW-OK

ACsns

Vdd

DFAULT

Dmon

Cout

Aout

Ainv

GND

PROG

Cinv

12Visns

5V/3V3isns

GND

-5V

Binv

Bout

12V

5V

3V3

-12V

VREF

PS-ON

PW-OK

ACsns

Vdd

DFAULT

Dmon

Cout

Aout

Ainv

GND

PROG

Cinv

12Visns

5V/3V3isns

GND

-5V