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L6610D 数据表(PDF) 5 Page - STMicroelectronics |
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L6610D 数据表(HTML) 5 Page - STMicroelectronics |
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5 / 29 page ![]() 5/29 L6610 17 -12V -12V UV/OV monitor. If connected to a voltage greater than 1.5V (e.g. VREF, #16), the function will be disabled. 18 -5V -5V UV/OV monitor. If connected to a voltage greater than 1.5V (e.g. VREF, #16), the function will be disabled. 19 GND Ground pin. The connection integrity of this pin is constantly monitored and in case of either a bond wire or a PCB trace going open, MFAULT (#1) and DFAULT (#11) will be forced high switching off the supply. 20 GND Ground pin. See above. 21 PROG The chip has 2 operating modes, depending on PROG input pin biasing: – normal mode: PROG should be floating or shorted to ground; – programming mode: forcing PROG high (+5V), the chip enters programming mode. PW_OK (#14) and PS_ON (#15) pins are disconnected from their normal functionality and they become inputs for DATA and CLOCK allowing the chip to be programmed. The programming mode al- lows selecting some options and adjusting some setpoints; 22 3V3 3V3 UV/OV monitor. It uses a separate reference to the feedback reference. 23 5V Input pin for 5V feedback, 5V current sense and 5V UV/OV monitor. 5V UV/OV uses a reference separate from that used for feedback. This pin connects the 5V part of the Main error amplifier feedback divider. 24 12V Input pin for 12V feedback, 12V current sense and 12V UV/OV monitor.12V UV/OV uses a reference separate from that used for feedback. This pin connects the 12V part of the Main error amplifier feedback divider. FUNCTION DESCRIPTION Name Description OVP Whenever one of the Main output voltages is detected going above its own OVP threshold, this function set MFAULT (#1) high latching the outputs off. The latch is released after cycling PS-ON (#15) switch or by reducing Vdd (#12) below the UV threshold. UVP Whenever one of the Main output voltages is detected going under its own UVP threshold, this function sets MFAULT (#1) high; if latch mode has been selected, this function will be latched. Otherwise an attempt will be made to restart the device after 1 second delay. If ACsns (#13) is low due to a brownout condition, UVP is disabled. OCP Whenever either the 5V (or 3V3, digitally selectable) or the 12V output experiences an overcurrent condition, the OCP function will force MFAULT (#1) high. If latch mode has been selected, this condition will be latched otherwise an attempt is made to restart the supply after a wait of 1 second. UVB Undervoltage blanking. When either converter is enabled, the relevant UV/OC monitoring circuits must not intervene to allow all outputs to come within tolerance. 64 ms timing is provided; for the auxiliary converter the timing starts as the IC has a valid supply, for the main converter it starts as the ACsns pin detects a valid input voltage for the converter. PW-OK delay PW-OK delay. After power-up, when the all of the monitored voltages are above their own UV threshold the PW-OK pin (#14) will be kept low for additional 250ms (typ.) to make sure all the outputs are settled. OFF delay Power-off delay. As soon as PS-ON (#15) pin is recognized high, indicating an imminent turn-off condition, PW-OK (#14) pin will go low immediately . The converter will be turned off after a delay of 2.5ms. PIN DESCRIPTION (continued) Pin # Name Description |
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