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L6660 数据表(PDF) 4 Page - STMicroelectronics

部件名 L6660
功能描述  MILLI-ACTUATOR DRIVER
PDF  9 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

L6660 数据表(HTML) 4 Page - STMicroelectronics

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OPERATIONAL AMPLIFIERS DESCRIPTION
Each driver has two output stages scaled in cur-
rent by a factor K = 10.
In voltage mode configuration the two outputs are
shorted.
In charge mode configuration OUT1 drives a ca-
pacitor Cint and is closed in feedback, while
OUTK drives the piezo, mirroring the current sup-
plied to Cint, with a current multiplied by a K fac-
tor (see Fig.2).
The supply voltage can be internally generated
by the DC-DC converter, or external, maintaining
the DC-DC converter in sleep mode (PIN3
shorted to ground), in this case the supply volt-
age can be 0 to V5/12+4 minimum value up to
70V in single supply or V5/12+4 to 35V symmetri-
cal to ground.
The drivers have 130dB DC gain and the Band-
width is 500KHz. Stability is guaranteed with a
minimum gain of 20dB, for a capacitive load in
the range 0.4nF up to 24nF.
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Vout0
OpAmp Output Voltage with 0V
Input Voltage
External feedback programmed
for DC gain value <30V/V
-1
+1
V
VrefOUT
Reference Voltage PIN13
2.4
2.5
2.6
V
Ivref
Reference Voltage Output Current
-1
+1
mA
Vref, cap
Filter capacitor at PIN13
10
100
nF
Vshifted
Voltage shift value
(VPIN11 - VPIN10)
1.0V
≤ Vin0-5 ≤ 3.5V
VrefIN
-2%
VrefIN
VrefIN
+2%
V
Shifter Gain
Analog Voltage Shifter DC
Voltage Gain
∆V10
V11
VPIN11 = VREFIN
→ V’10
VPIN11 = VREFIN + 0.1V
→ V"10
G
=
V’’10 − V’10
0.1
0.975
1.00
1.025
BWVshift
Shifter circuitry Band Width
3dB amplitude drop
2
MHz
VrefIN
External reference voltage
(PIN14)
2.0
2.6
V
Isleep
Total current in Sleep Mode
PIN7 at 0 logic
800
µA
EAoff
DC-DC converter Error
Amplifier Input voltage Offset
(VPIN14-VPIN21)
VrefIN = 2.25V
-12
+12
mV
IEA
Error amplifier Current
Capability
±100
µA
HVP%
Total HVP precision
Vref = 2.25V
±0%
-4
+4
%
Vlogic0
Voltage level for 0 logic at
digital input pin (Pin 1-4-7-15)
0.9
V
Vlogic1
Voltage level for 1 logic at
digital input pin (Pin 1-4-7-15)
1.6
V
Ztime
Decay period for
∆V = |19V|
Vref (Pin14) = 2.25V See Fig. 3
0°C < Tcase < 80°C
140
340
µs
Top
Operative period from Not
Selected phase to Selected
phase for each driver
4
µs
Note 1: Selectable by external resistors.
Note 2: Set by external Coil and Capacitor from 80 to 550KHz.
Note 3: Take into account the total power dissipation.
ELECTRICAL CHARACTERISTICS (continued)
22
24
26
28
30
32
34
36
1 59 13 17 21 25 29 33 37 41 45 49 53 57 61 65
Load DC Current (mA)
12V
11V
10V
9V
8V
7V
6V
5V
Figure 1. Load Regulation
L6660
4/9



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