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quency after a load transient as well as to mask PWM comparator output against noise and spikes.

The system has not an internal clock, because this is a hysteretic controller, so the turn on pulse will start if three

conditions are met contemporarily: the FB pin voltage is lower than the reference voltage, the minimum off time

is passed and the current limit comparator is not triggered (i.e. the inductor current is below the current limit

value). The voltage on the OSC pin must range between 50mV and 2V to ensure the system linearity.

1.2 Closing the loop

The loop is closed connecting the output voltage (or the output divider middle point) to the FB pin. The FB pin

is linked internally to the comparator negative pin and the positive pin is connected to the reference voltage

(0.9V Typ.) as in Figure 2. When the FB goes lower than the reference voltage, the PWM comparator output

goes high and sets the flip-flop output, turning on the high side MOSFET. This condition is latched to avoid noise

spike. After the on-time (calculated as described in the previous section) the system resets the flip-flop and then

turns off the high side MOSFET and turns on the low side MOSFET. Internally the device has more complex

logic than a flip-flop to manage the transition in correct way. For more details refers to the Figure 1.

The voltage drop along ground and supply metals connecting output capacitor to the load is a source of DC

error. Further the system regulates the output voltage valley value not the average, as in the Figure 3 is shown.

So the voltage ripple on the output capacitor is a source of DC static error (as the PCB traces). To compensate

the DC errors, an integrator network must be introduced in the control loop, by connecting the output voltage to

the INT pin through a capacitor and the FB pin to the INT pin directly as in Figure 4. The internal integrator am-

for output ripple.

Figure 3. Valley regulation

The integrator amplifier generates a current, proportional to the DC errors, that increases the output capacitance

voltage in order to compensate the total static errors. A voltage clamper within the device forces INT pin voltage

transient. Also, this means that the integrator is capable of recovering output error due to ripple when its peak-

to-peak amplitude is less than 150mV in steady state.

ground to reduce ripple amplitude at INT pin, otherwise the integrator can operate out of its linear range. Choose

Eq 5

where GINT=50 µs is the integrator transconductance,

is given by:

Time

Vout

Vref

<Vout>

DC Error Offset

C

IN T1

g

IN T

α

OUT

⋅

2

π F

u

⋅⋅

----------------------------------

=