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latched after the 16th SCLK pulse. If less than 16 clock pulses are provided before SDEN goes low, the data

transfer is aborted.

All transfers are shifted into the serial port LSB first. The first byte of the transfer is for Address and Instruction

information. The first bit is R/W instruction bit, 0 is for WRITE and 1 is for READ. Following 3 bits are for

Combo Data Bank (all set to ‘1’). The last 4 bits are for Register Address.

Figure 2. Serial Port Data Transfer Format

INTERNAL REGISTERS DEFINITION

Reg:

0

Name:

Spindle Spin-Up Register

Type:

Write only

Address: 0Eh

BIT

LABEL

DESCRIPTION

0

START

“0” Reset and Brakes the Spindle. “1” Initiates the Spindle Start-Up

procedure.

1

EXTERNAL

“0” Spindle BEMF processing in internal mode. “1” External mode.

2

SEQINC

In external mode, a “0” to ”1” transition, increments the Spindle

Sequencer.

3

STOP

“0” Complete Internal Spindle Start-Up. “1” Stop after Inductive Sense

4

INDSENSE

“0” Normal condition. “1” in External mode, initiate the Inductive

Sense

5

SPCOAST

“0” Spindle Outputs Enabled. “1” Disabled.

6

SPINUPTIME 0

Spindle Internal Spin Up.

Bit 7

Bit 6

Time

Energization Time. First Bit.

0

0

10mS

7

SPINUPTIME 1

Spindle Internal Spin Up.

0

1

20mS

Energization Time. Second Bit.

1

0

30mS

1

1

40mS

SCLK

SDATA

SDEN

INSTRUCTION (READ/WRITE), 1BIT

ADDRESS, 4 BITS

ADDRESS, COMBO DATA BANK, 3 BITS

DATA, 8 BITS