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L7200

BIT

LABEL

DESCRIPTION

4

INDEX

External FLL update.

5

EXTK

“0” Spindle Speed internal KFLL. “1” All Reg#7 and Lsb of Reg#8 bits are

mixed to allow external setting of KFLL.

6

MECH/ELEC

Electrical or Mechanical cycle for Spindle FLL control.

“0” Mechanical. “1” Electrical.

7

8_12POLE

Spindle Motor Poles. “0” 8 poles. “1” 12 poles.

Reg:

3

Name:

Spindle Set-Up 2 Register

Type:

Write only

Address: 3Eh

BIT

LABEL

DESCRIPTION

0

ZCWINDOW

Chop cycle for Spindle ZC tristate time. “0” Two. “1” One.

1

REVBRAKE

“1” Spindle Reverse Brake. Toggling this bit will define the time before

ending over normal brake. 1 = 10mS. 2 = 20mS. 3 = 40mS.

2

CLKDIV

SYSCLK divider. “0” SYSCLK. “1” SYSCLK divide by 2.

3

DIV1.5

SYSCLK divider. “0” SYSCLK. “1” SYSCLK divide by 1.5.

4

FLLCOARSE<0>

LSB of Spindle FLL Coarse Counter.

5

FLLCOARSE<1>

Bit 1 of Spindle FLL Coarse Counter.

6

FLLCOARSE<2>

Bit 2 of Spindle FLL Coarse Counter.

7

FLLCOARSE<3>

Bit 3 of Spindle FLL Coarse Counter.

Reg:

4

Name:

Spindle FLL Coarse Register

Type:

Write only

Address: 4Eh

BIT

LABEL

DESCRIPTION

0

FLLCOARSE<4>

Bit 4 of Spindle FLL Coarse Counter.

1

FLLCOARSE<5>

Bit 5 of Spindle FLL Coarse Counter.

2

FLLCOARSE<6>

Bit 6 of Spindle FLL Coarse Counter.

3

FLLCOARSE<7>

Bit 7 of Spindle FLL Coarse Counter.

4

FLLCOARSE<8>

Bit 8 of Spindle FLL Coarse Counter.

5

FLLCOARSE<9>

Bit 9 of Spindle FLL Coarse Counter.

INTERNAL REGISTERS DEFINITION (continued)