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ADGM3144BCCZ-R2 数据表(PDF) 6 Page - Analog Devices

部件名 ADGM3144BCCZ-R2
功能描述  3mm × 3mm SP4T MEMS Switch, 0Hz/DC to 30GHz
PDF  30 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADGM3144BCCZ-R2 数据表(HTML) 6 Page - Analog Devices

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Data Sheet
ADGM3144
SPECIFICATIONS
analog.com
Rev. 0 | 6 of 30
1 Typical specifications tested at 25°C with VDD = 3.3V.
2 RFx is RF1, RF2, RF3, and RF4. INx is IN1, IN2, IN3, and IN4.
3 This value shows the time it takes for 1% of a sample lot to fail.
4 Switch is settled after 200µs. Do not apply RF power between 0µs to 200µs.
5 RF power should be removed or less than 5dBm, 50µs before turning the switch off.
6 Spectrum analyzer setup: resolution bandwidth (RBW) = 200Hz, video bandwidth (VBW) = 2Hz, span = 100kHz, input attenuator = 0dB, detector type = peak, maximum
hold = off. Measurements taken with one switch on and off switch port terminated into 50Ω. The fundamental feedthrough noise or harmonic thereof is tested (whichever is
the highest).
7 The on leakage and off leakage specifications depend on the DC voltage level applied to the switch node. For example, if 1V is applied at RFx to RFC, the on leakage
specification is 0.2µA and off leakage specification is 0.1µA. The leakage specification of the switch is mainly driven by the internal 10MΩ resistors to ground connected on
all the RF nodes to avoid floating nodes.
TIMING CHARACTERISTICS
VDD = 3.0V to 3.6V, GND = 0V and all specifications TMIN to TMAX, unless otherwise noted.
Table 2. Timing Characteristics
Parameter
Limit at TMIN
Limit at TMAX
Unit
Conditions
t1
100
ns
SCLK period
t2
45
ns
SCLK high pulse width
t3
45
ns
SCLK low pulse width
t4
25
ns
CS falling edge to SCLK active edge
t5
20
ns
Data setup time
t6
20
ns
Data hold time
t7
25
ns
SCLK active edge to CS rising edge
t8
20
ns
CS falling edge to SDO data available
t91
40
ns
SCLK falling edge to SDO data available
t10
25
ns
CS rising edge to SDO data available
t11
100
ns
CS high time between SPI commands
t12
25
ns
SCLK edge rejection to CS falling edge
t13
25
ns
CS rising edge to SCLK edge rejection
1 Measured with a 20pF load. t9 determines the maximum SCLK frequency when SDO is used.
Timing Diagrams
Figure 2. Addressable Mode Timing



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