ADGM3144BCCZ-R2 datasheet(21/30 Pages) AD

21 / 30 page

Data Sheet

ADGM3144

THEORY OF OPERATION

analog.com

Rev. 0 | 21 of 30

SPI DIGITAL INTERFACE

The ADGM3144 can be controlled through an SPI digital interface

when Pin 19 (PIN/SPI) is high. SPI Mode 0 or Mode 3 can be

used with the device, and it operates with SCLK frequencies up to

10MHz. The default mode when the SPI is active is the addressable

mode, in which the devices registers are accessed by a 16-bit SPI

command bounded by the state of CS. The ADGM3144 can also

operate in the daisy-chain mode.

The SPI pins of the ADGM3144 are CS, SCLK, SDI, and SDO.

Hold CS low when using the SPI. Data is captured on SDI on

the rising edge of SCLK and data is propagated out on SDO

on the falling edge of SCLK. SDO has a push-pull output driver

architecture. So, it does not require pull-up resistors. When not

pulled low by the ADGM3144, SDO is in a high-impedance state.

Addressable Mode

The addressable mode is the default mode for the ADGM3144

upon power up. A single SPI frame in the addressable mode is

bound by a CS falling edge and the succeeding CS rising edge. It

comprises 16 SCLK cycles. Figure 58 shows the timing diagram for

addressable mode for SPI Mode 0.

The first SDI bit indicates if the SPI command is a read or write

command. The next seven bits determine the target register ad-

dress. The remaining eight bits provide the data to the addressed

during these clock cycles SDO propagates out the data contained

in the addressed register.

In Mode 0, during any SPI command, SDO sends out eight align-

ment bits on the CS falling edge and the first seven SCLK falling

edges (in Mode 3, the first SCLK falling edge is ignored, as shown

in Figure 59). The alignment bits observed at SDO are 0x25.

The target register address of an SPI command is determined on

the eighth SCLK rising edge. Data from this register propagates out

on SDO from the eighth to the fifteenth SCLK falling edge during

SPI reads. A register write occurs on the 16th SCLK rising edge

during SPI writes.

Figure 58. Addressable Mode Timing Diagram (Mode 0)

Figure 59. Addressable Mode Timing Diagram (Mode 3)

Daisy-Chain Mode

The connection of several ADGM3144 devices in a daisy-chain

configuration is possible. All devices share the same CS and SCLK

line while the SDO of a device forms a connection to the SDI of the

next device, creating a shift register. In the daisy-chain mode, SDO

is an 8-cycle delayed version of SDI.

The ADGM3144 may only enter the daisy-chain mode from the ad-

dressable mode by sending the 16-bit SPI command, 0x2500. See

Figure 60 for an example of this. When the ADGM3144 receives

this command, the SDO of devices sends out the same command.

This is because the alignment bits at SDO are 0x25. This allows

multiple daisy-connected devices to enter the daisy-chain mode

in a single SPI frame. A hardware reset is required to exit the

daisy-chain mode.

For the timing diagram of a typical daisy-chain SPI frame, see

Figure 61. When CS goes high, Device1 writes Command0 [7:0]

to its switch data register, Device 2 writes Command1 [7:0] to its

switches, and so on. The SPI block uses the last eight bits it

received through SDI to update the switches. After entering the

daisy-chain mode, the first eight bits sent out by SDO are 0x00.

When CS goes high, the internal shift register value does not reset

to zero.

An SCLK rising edge reads in data on SDI while data is propagated

out SDO on an SCLK falling edge. The expected number of SCLK

cycles should be a multiple of eight before CS goes high. When this

is not the case, the SPI sends the last eight bits received to the

switch data register.

Figure 60. SPI Command to Enter the Daisy-Chain Mode

Figure 61. Example of an SPI Frame When Three ADGM3144 are Connected

in the Daisy-Chain Mode

Hardware Reset

The digital section of the ADGM3144 goes through an initialization

phase during VDD power up. To hardware reset the part, power

cycle the VDD input. After power-up or a hardware reset, ensure

there is a minimum of 10µs from the time of power-up or reset

before any SPI command is issued. Ensure that VDD does not drop

out during the 10µs initialization phase because it may result in

incorrect operation of the ADGM3144.

ADGM3144BCCZ-R2 数据表(PDF) 21 Page - Analog Devices

ADGM3144BCCZ-R2 数据表(HTML) 21 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

数据表下载