TLV803ED18DPWR datasheet(21/52 Pages) TI2

21 / 52 page

9.2.2 Detailed Design Procedure

Select the TLV803EA29DBZR to satisfy the voltage threshold requirement for 3.3-V rail monitoring. As

mentioned in Table 12-1, the TLV803EA29DBZR triggers an undervoltage fault at the RESET output when

VDD falls below VIT- which is 2.93 V for this device variant. Place a pull-up resistor on RESET to VDD to satisfy

the output logic requirement while not violating the IRESET recommended limit.

9.2.3 Application Curves

Figure 9-2 and Figure 9-3 show the TLV803EA29 functionality. In Figure 9-2, the VDD supply voltage drops

from 30% above VIT- = 3.8 V to 10% below VIT- = 2.6 V with a 0.1-µF capacitor on VDD. The RESET output

is connected to VDD through the pull-up resistor so when the VDD supply voltage drops. The RESET output

discharges down to the VDD supply voltage through the pull-up resistor and RESET pin capacitance. Once the

high-to-low propagation delay tPD_HL expires, the internal MOSFET turns on and asserts RESET to logic low.

Note that tPD_HL varies with VDD specifically on how much VDD drops and how quickly in addition to the VDD

and RESET pin capacitances. In Figure 9-3, VDD rises from 2 V to 4 V and the RESET output deasserts to logic

high after the reset delay time (tD) expires.

VDD

RESET

Propagation Delay from VDD falling below VIT- to Reset

(tPD_HL) = 25 µs

Figure 9-2. Propagation Delay when Fault Occurs

after VDD Falls Below VIT- (TLV803EA29 No

Load) (1) (2)

VDD

RESET

Reset Delay (tD) = 200 ms

Figure 9-3. RESET Delay when Returning from

Fault after VDD Rises Above VIT+ (TLV803EA29)

1. Typical tPD_HL= 30 µs for VDD falling from (VIT+ + 30%) to (VIT- - 10%).

2. VDD does not fall all the way to 0 V so RESET momentarily discharges to VDD until tPD_HL expires.

www.ti.com

TLV803E, TLV809E, TLV810E

SLVSES2J – AUGUST 2018 – REVISED MAY 2021

Submit Document Feedback

Product Folder Links: TLV803E TLV809E TLV810E

TLV803ED18DPWR 数据表(PDF) 21 Page - Texas Instruments