L9823

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Output Stages Control

Each output is controlled with its latch and with a common Reset line, which enables all outputs.

The control data are transmitted via the SI input, the timing of the serial interface is shown in Fig. 1.

The device is selected with low CSB signal and the input data are transferred into the 8 bit shift register at every

falling SCLK edge. The rising edge of the CSB latches the new data from the shift register to the drivers.

Figure 1. Timing of the Serial Interface

The SPI register data are transferred to the output latch at rising CSB edge. The digital filter between CSB and

the output latch ensures that the data are transferred only after 8 SCLK cycles or multiple of 8 SCLK cycles

since the last CSB falling edge. The CSB changes only at low SCLK.

Diagnostics

The output voltage at all outputs is compared with the diagnostic threshold, typ 0,55

Diagnostic Table for outputs:

Fault condition 1) "output short circuit to Vbat" : For SFPD = Low the output was switched on and the voltage at

the output exceeded the diagnostics threshold due to overcurrent, the output overload latch was set and the

output has been switched off. The diagnostic bit is high.

: For SFPD = High the output was switched on and the voltage at the output exceeds the diagnostics threshold.

The output operates in current regulation mode or has been switched off due to thermal shutdown. The status

bit is high.

Fault condition 2) "open load" or "output short circuit to GND" : the output is switched off and the voltage at the

output drops below the diagnostics threshold, because the load current is lower than the output diagnostic cur-

rent source, the load is interrupted. The diagnostic bit is low.

At the falling edge of CSB the output status data are transferred to the shift register. When SCB is low, data bits

contained in the shift register are transferred to SO output at every rising SCLK edge.

Output

Output-voltage

Status-bit

Output-mode

off

> DG-threshold

high

correct operation

off

< DG-threshold

low

fault condition 2)

on

< DG-threshold

low

correct operation

on

> DG-threshold

high

fault condition 1)

CSB

SCLK

SI

SO

tsclch

thclcl

tclh

tcll

tsclcl

thclch

tcsdv

tpcld

tpchdz

not defined

D7

D0

tscld

thcld

D7

D6

D0