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L9823 数据表(PDF) 6 Page - STMicroelectronics |
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L9823 数据表(HTML) 6 Page - STMicroelectronics |
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6 / 12 page ![]() L9823 6/12 Outputs Control Tables : tdoff Turn OFF delay CSB = 50% to RL = 50Ω VOUT = 0,1·Vbat, Vbat = 16V 20 µs dVon/dt Turn ON voltage slew-rate 90% to 30% of Vbat; RL = 50Ω; Vbat = 16V 0.7 2.1 3.5 V/µs dVoff/dt Turn OFF voltage slew-rate 30% to 90% of Vbat; RL = 50Ω; Vbat = 16V 0.7 2.1 3.5 V/µs dVoff clamp/dt Turn OFF voltage clamp slew-rate 30% to 80% of VOUT clamp RL = 500Ω 0.7 2.1 5.5 V/µs Serial diagnostic link (Load capacitor at SO = 200pF) fsclk Clock frequency 50% duty cycle 3 MHz tclh Minimum time SCLK = HIGH 160 ns tcll Minimum time SCLK = LOW 160 ns tpcld Propagation delay SCLK to data at SO valid 4.9V ≤ VDD ≤ 5.1V 100 ns tcsdv CSB = LOW to data at SO active 100 ns tsclch SCLK low before CSB low Setup time SCLK to CSB change H/L 100 ns thclcl SCLK change L/H after CSB = Low Setup time CSB to SCLK change L/H 100 ns tscld SI input setup time SCLK change H/L after SI data valid 20 ns thcld SI input hold time SI data hold after SCLK change H/L 20 ns tsclcl SCLK low before CSB high 150 ns thclch SCLK high after CSB high 15, ns tpchdz CSB L/H to output data float 100 ns tReset Minimum Reset time Reset = Low 160 ns Outputs: SI-bit 0 1 Output on off Symbol Parameter Test Condition Min. Typ. Max. Unit ELECTRICAL CHARACTERISTCS (continued) |
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