GD32H757VMT7 datasheet(63/151 Pages) GIGADEVICE

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GD32H757xx Datasheet

Functional description

3.1.

Arm® Cortex®-M7 core

The Arm® Cortex®-M7 processor is a highly efficient high-performance, embedded processor

that features low interrupt latency, low-cost debug, and has backwards compatibility with

existing Cortex-M profile processors. The processor has an in-order super-scalar pipeline that

means many instructions can be dual-issued, including load/load and load/store instruction

pairs because of multiple memory interfaces. The Cortex-M7 is a high-performance processor,

which features a 6-stage superscalar pipeline with branch prediction and an optional FPU

capable of single-precision and optionally double-precision operations. The instruction and

data buses have been enlarged to 64-bit wide over the previous 32-bit buses.

The interfaces that the processor supports include:



64-bit AXI4 interface.



32-bit AHB master interface.



32-bit AHB slave interface.



64-bit instruction TCM interface.



2x32-bit data TCM interfaces.

The processor contains the following external interfaces:



AHBP interface.



AHBS interface.



AHBD interface.



External Private Peripheral Bus.



ATB interfaces.



TCM interface.



Cross Trigger interface.



MBIST interface.



AXIM interface.

32-bit Arm® Cortex®-M7 processor core



Up to 600 MHz operation frequency.



Single-cycle multiplication and hardware divider.



Integrated DSP instructions.



24-bit SysTick timer.

The Cortex®-M7 processor is based on the ARMv7-M architecture and supports a powerful

and scalable instruction set including general data processing I/O control tasks, advanced

data processing bit field manipulations, DSP and floating point instructions. Some system

peripherals listed below are also provided by Cortex®-M7:



Nested Vectored Interrupt Controller (NVIC).

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