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GD32H757VMT7 数据表(PDF) 137 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD32H757VMT7 数据表(HTML) 137 Page - GigaDevice Semiconductor (Beijing) Inc. |
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137 / 151 page ![]() GD32H757xx Datasheet 136 Table 4-79. SDRAM read timings Symbol Parameter Min Max Unit tw(SDCLK) EXMC_SDCLK period 2 Tfclk − 0.5 2 Tfclk +0.5 ns tsu(SDCLKH _Data) Data input setup time 3.5 — th(SDCLKH_Data) Data input hold time 0 — td(SDCLKL_Add) Address valid time — 2.5 td(SDCLKL- SDNE) Chip select valid time — 2.5 th(SDCLKL_SDNE) Chip select hold time 0 — td(SDCLKL_NRAS) NRAS valid time — 2 th(SDCLKL_NRAS) NRAS hold time 0 — td(SDCLKL_NCAS) NCAS valid time — 2 th(SDCLKL_NCAS) NCAS hold time 0 — 4.34. TIMER characteristics Table 4-80. TIMER characteristics(1) Symbol Parameter Conditions Min Max Unit tres Timer resolution time — 1 — tTIMERxCLK fTIMERxCLK = 300 MHz 3.3 — ns fEXT Timer external clock frequency — 0 fTIMERxCLK/2 MHz fTIMERxCLK = 300 MHz 0 333 MHz RES Timer resolution TIMER0 & TIMER2 & TIMER3 & TIMER7& TIMER14 & TIMER15 & TIMER16 & TIMER30 & TIMER31 & TIMER40 & TIMER41 & TIMER42 & TIMER43 & TIMER44 — 16 bit TIMER1 & TIMER4 & TIMER5 & TIMER6 & TIMER22 & — 32 bit |
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