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STM32L4P5CEU6P 数据表(PDF) 269 Page - STMicroelectronics |
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STM32L4P5CEU6P 数据表(HTML) 269 Page - STMicroelectronics |
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269 / 311 page  DS12903 Rev 2 269/311 STM32L4P5xx Electrical characteristics 277 6.3.30 Camera interface (DCMI) timing specifications Unless otherwise specified, the parameters given in Table 118 for DCMI are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage summarized in Table 20, with the following configuration: • DCMI_PIXCLK polarity: falling • DCMI_VSYNC and DCMI_HSYNC polarity: high • Data format: 14 bits • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 x VDD Figure 66. DCMI timing diagram Table 118. DCMI characteristics(1) Symbol Parameter Condition Min Max Unit - Frequency ratio DCMI_PIXCLK/fHCLK -- 0.4 - DCMI_PIXCLK Pixel clock input 1.71 < VDD < 3.6 Voltage range V1 -48 MHz 1.71 < VDD < 3.6 Voltage range V2 -10 Dpixel Pixel clock input duty cycle - 30 70 % MS32414V2 DCMI_PIXCLK tsu(VSYNC) tsu(HSYNC) DCMI_HSYNC DCMI_VSYNC DATA[0:13] 1/DCMI_PIXCLK th(HSYNC) th(HSYNC) tsu(DATA) th(DATA) |
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