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STM32L4P5CEU6P 数据表(PDF) 270 Page - STMicroelectronics |
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STM32L4P5CEU6P 数据表(HTML) 270 Page - STMicroelectronics |
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270 / 311 page ![]() Electrical characteristics STM32L4P5xx 270/311 DS12903 Rev 2 6.3.31 Parallel slave interface (PSSI) Unless otherwise specified, the parameters given in Table 119 for PSSI are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage summarized in Table 21, with the following configuration: • PSSI_PDCK polarity: falling • PSSI_RDY and PSSI_DE polarity: low • Data format: 16 bits • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 x VDD tsu(DATA) Data input setup time 1.71 < VDD < 3.6 Voltage range V1 3- ns 1.71 < VDD < 3.6 Voltage range V2 4- th(DATA) Data hold time 1.71 < VDD < 3.6 Voltage range V1 0.5 - 1.71 < VDD < 3.6 Voltage range V2 0.5 - tsu(HSYNC), tsu(VSYNC) DCMI_HSYNC/DCMI_VSYNC input setup time 1.71 < VDD < 3.6 Voltage range V1 2- 1.71 < VDD < 3.6 Voltage range V2 3- th(HSYNC), th(VSYNC) DCMI_HSYNC/DCMI_VSYNC input hold time 1.71 < VDD < 3.6 Voltage range V1 0.5 - 1.71 < VDD < 3.6 Voltage range V2 0.5 - 1. Guaranteed by characterization results. Table 118. DCMI characteristics(1) (continued) Symbol Parameter Condition Min Max Unit |
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