MP9989

– FAST TURN-OFF INTELLIGENT RECTIFIER

MP9989 Rev. 1.1

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11

8/27/2020

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is the peak reverse current and tF is the reverse

current fall time.

The total loss of the MP9989 (PLOSS) is the sum

of the above losses. If a RC snubber is used, the

power loss caused by this snubber must also be

taken into consideration.

The junction and case temperature rises can be

calculated with the thermal resistance of the

junction-to-ambient (

θJA) and junction-to-case

(

θJC). The junction temperature must be within

ABS (typically 150°C). Calculate

∆TJA and ∆TJC

with Equation (4) and Equation (5):





 

JA

LOSS

JA

TP

(4)





 

JC

LOSS

JC

TP

(5)

The thermal resistance can be reduced in one of

several ways to lower the temperature: a thicker

copper layer attached to VD and VS, additional

vias for thermal dissipation, or heatsinks. The

real maximum output current can be set

combining the real tested data.

PCB Layout Guidelines

Efficient

PCB

layout

is

critical for

stable

operation. For best results, refer to Figure 5,

Figure 6, Figure 7, and follow the guidelines

below.

1. Connect SENSE pin to different position for

an adjustable turn-off point of time during the

fast transients in CCM. In general, the farther

the junction point is from the VD, the earlier

the SR turns off. (See Figure 5).

2. Keep the IC out of the power loop to prevent

the sensing loop and power loop from

interrupting each other.

VDD

VD

SENSE

VS

Decoupling

Capacitor

Sense Position

Figure 5: Voltage Sensing for VD/SENSE

3. Place a decoupling ceramic capacitor from

VDD to VS close to the IC for adequate

filtering.

Layout Example

Figure 6 and Figure 7 show the layout example

for QFN4x5-8 package and SOIC-8 package in

high-side application of flyback power supply,

respectively. It is a single layer with a through-

hole transformer. R2 and C2 are the RC snubber

network for the internal MOSFET. The sensing

loop (SENSE to the MOSFET drain) is optimized

and kept separate from the power loop. The VDD

decoupling capacitor (C1) is placed beside VDD.

Figure 6: Layout Example for QFN4x5-8 package

in Flyback High-Side Application

Figure 7: Layout Example for SOIC-8 package in

Flyback High-Side Application