Symbol

I/O voltage

I/O

Description

Ball

V2V5_OUT

2.5 V

PWR LDO core 2.5 V output

F5

GND_PMU

GND

GND Main voltage regulator ground

G2

GND_BKP_PMU

GND

GND Backup voltage regulator ground

P5

GND_TSENS

GND

GND Temperature sense block ground

D10

GND_RF

GND

GND RF ground

P9, R9, M8, N8, P8, R8

GND

GND

GND Ground

F8, M7, N6, M4, E3, E4, T3,

F2

LDO_1V1_OUT_0(2)

1.1 V

PWR LDO 1.1 V OUT_0

A1

PLL_VCCp_0(2)

1.2 V

PWR RF VCC_0 power input

A3

LDO_RF_OUT_1V1_0(2)

1.1 V

PWR LDO RF_0 power output

A4

LDO_IN_3V3_1V8_0(2)

1.70 or 3.6 V PWR LDO RF_0 power input - (LDO_RFin_0)

A5

RFA_IF_VCC_0(2)

1.2 V

PWR RFA_IF_VCC_0

A7

LNA_VCC_0(2)

1.2 V

PWR LNA_VCC_0

A9

RF_GND_0(2)

GND

GND RF_GND_0

B5, B6, B7, B8, B9, C7

GND_0(2)

GND

GND GND_0

B4, C4, D3, D5

LDO_1V8_OUT_0(2)

1.8 V

PWR LDO_1V8_OUT_0

B1

LDOS_VCC_0(2)

3 to 3.6 V

PWR LDO_0 power input

C1

LNA_GND_0

GND

GND LNA ground

A10, C10

1. Backup power shall be applied at the same time or before VCORE_IN, not after.

2. Pins names with trailing _0 are related to RF chip.

Table 2. Main function pins

Symbol

I/O voltage(1)

I/O

Description

Ball Reset state

EXT_REG_SEL

VCORE_IN

I

LDO core disable.

When high, the LDO Core is off. The Core must be supplied by

an external power through VDD_EXT_REG balls.

C3

NA

TEST

IOring2

I

TEST - JTAG enable. In mission/application mode this pin must

be connected to GND.

D4

Hi-Z/PD

RTC_XTI

VBK_IN/IOring0

I

If 32 kHz oscillator is enabled then input of the 32 kHz oscillator

amplifier circuit. Else CMOS input as electrical characteristic

table. Both cases, it is the reference for real time clock counter

circuitry.

T5

NA

RTC_XTO

VBK_IN/IOring0 O Output of the oscillator amplifier circuit.

T6

NA

RESETn

VBK_IN/IOring0

I

Reset input with Schmitt-Trigger characteristics and noise.

R5

Hi-Z/PD

WAKEUP

VBK_IN/IOring0

I

When high, the device will wakeup and exit from standby mode. It

has higher priority compared to Standby_in pin. Wakeup from

standby mode.

P6

Hi-Z

STANDBY_IN(2) VBK_IN/IOring0

I

When low, the chip is forced in standby mode.

R7

Hi-Z

STANDBY_OUT

VBK_IN

O When low, it indicates the device is in standby mode.

P7

Hi-Z

1. In standby mode , if VIO1 and VIO2 are powered, GPIOs have no driving capabilities and no PD/PU is active.

2. If VCORE_IN is removed before STANDBY_IN has switched from high to low, STANDBY_OUT remains high level, even if

device enters in standby mode.

STA8135G

Block diagram and pin description

DS14788 - Rev 1

page 5/41