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SN0400ALK-DC 数据表(PDF) 39 Page - Texas Instruments |
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SN0400ALK-DC 数据表(HTML) 39 Page - Texas Instruments |
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39 / 126 page  4.12.2 TX Typical Characteristics at 1.8GHz (continued) Typical values at TA = +25°C with nominal supplies. Default conditions: TX input data rate = 491.52MSPS, fDAC = 11796.48MSPS (24x interpolation), interleave mode, 1st Nyquist zone output, PLL clock mode with fREF = 491.52MHz, AOUT = –1 dBFS, DSA = 0dB, Sin(x)/x enabled, DSA calibrated DSA (dB) 0 4 8 12 16 20 24 28 32 36 40 -0.02 -0.01 0 0.01 0.02 0.03 0.04 0.05 1TX 2TX 3TX 4TX fDAC = 5898.24MSPS, interleave mode, matching at 1.8GHz Differential Phase Error = PhaseOUT(DSA Setting – 1) – PhaseOUT(DSA Setting) Figure 4-54. TX Uncalibrated Differential Phase Error vs DSA Setting and Channel at 1.8GHz DSA (dB) 0 4 8 12 16 20 24 28 32 36 40 -0.25 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0.25 1TX 2TX 3TX 4TX fDAC = 8847.36MSPS, straight mode, matching at 2.6GHz Differential Phase Error = PhaseOUT(DSA Setting – 1) – PhaseOUT(DSA Setting) Phase DNL spike may occur at any DSA setting. Figure 4-55. TX Calibrated Differential Phase Error vs DSA Setting and Channel at 1.8GHz DSA (dB) 0 4 8 12 16 20 24 28 32 36 40 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 1TX 2TX 3TX 4TX fDAC = 5898.24MSPS, interleave mode, matching at 1.8GHz Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Setting = 0) Figure 4-56. TX Uncalibrated Integrated Phase Error vs DSA Setting and Channel at 1.8GHz DSA (dB) 0 4 8 12 16 20 24 28 32 36 40 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 1TX 2TX 3TX 4TX fDAC = 5898.24MSPS, interleave mode, matching at 1.8GHz Integrated Phase Error = Phase(DSA Setting) – Phase(DSA Setting = 0) Figure 4-57. TX Calibrated Integrated Phase Error vs DSA Setting and Channel at 1.8GHz www.ti.com AFE7950-SP SBASAG7A – MARCH 2024 – REVISED AUGUST 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: AFE7950-SP |
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