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PRELIMINARY
CY28323
Document #: 38-07004 Rev. *B
Page 20 of 22
Layout Example
FB
+3.3V Supply
0.005
µF
G
G
VDDQ3
C3
48
47
46
45
44
43
42
41
40
38
37
36
35
34
3
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
39
G
V
G
V
G
V
G
V
G
V
G
V
G
V
G
G
5
Ω
VDDQ3
C5
C6
G = VIA to GND plane layer
V =VIA to respective supply plane layer
Note: Each supply plane or strip should have a ferrite bead and capacitors
Cermaic Caps C3 = 10–22
µF
C4 = 0.005
µF
FB = Dale ILB1206 - 300 (300
Ω @ 100 MHz)
C5 = 10
µF C6 = 0.1 µF
All bypass caps = 0.1
µF ceramic
* For use with onboard video using 48 MHz for Dot Clock or connect to VDDQ3
*
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G