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CY28323PVC 数据表(PDF) 3 Page - Cypress Semiconductor

部件名 CY28323PVC
功能描述  FTG for Intel짰 Pentium짰 4 CPU and Chipsets
PDF  22 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor

CY28323PVC 数据表(HTML) 3 Page - Cypress Semiconductor

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PRELIMINARY
CY28323
Document #: 38-07004 Rev. *B
Page 3 of 22
24_48MHz/FS1
23
I/O
24- or 48-MHz Output/Frequency Select 1: 3.3V fixed 24-MHz or 48-MHz
non-spread spectrum output. This pin also serves as a power-on strap option to
determine device operating frequency as described in Table 4.
This output will be used as the reference clock for SIO devices in Intel 845
(Brookdale) platforms. For Intel Brookdale - G platforms, this output will be used
as the reference clock for both USB host controller and SIO devices. We recom-
mend system designer to configure this output as 48 MHz and “HIGH Drive” by
setting Byte [5], Bit [0] and Byte [9], Bit [7], respectively.
PWR_DWN#
42
I
Power Down Control: 3.3V LVTTL-compatible input that places the device in
power-down mode when held LOW.
SCLK
26
I
SMBus Clock Input: Clock pin for serial interface.
SDATA
25
I/O
SMBus Data Input: Data pin for serial interface.
RST#
20
O
(open-
drain)
System Reset Output: Open-drain system reset output.
IREF
35
I
Current Reference for CPU Output: A precision resistor is attached to this pin
which is connected to the internal current reference.
VTT_PWRGD#
19
I
Powergood from Voltage Regulator Module (VRM): 3.3V LVTTL input.
VTT_PWRGD# is a level-sensitive strobe used to determine when FS0:4 and
MULTSEL0:1 inputs are valid and OK to be sampled (Active LOW). Once
VTT_PWRGD# is sampled LOW, the status of this input will be ignored.
VDD_REF,
VDD _PCI,
VDD_48MHz,
VDD_3V66,
VDD_CPU
2, 9, 18, 24,
32, 39, 46
P
3.3V Power Connection: Power supply for CPU outputs buffers, 3V66 output
buffers, PCI output buffers, reference output buffers and 48-MHz output buffers.
Connect to 3.3V.
GND_PCI,
GND_48MHz,
GND_3V66,
GND_CPU,
GND_REF,
5, 13, 21, 29,
36, 43, 47
G
Ground Connection: Connect all ground pins to the common system ground
plane.
VDD_CORE
34
P
3.3V Analog Power Connection: Power supply for core logic, PLL circuitry. Con-
nect to 3.3V.
GND_CORE
33
G
Analog Ground Connection: Ground for core logic, PLL circuitry.
Pin Definitions (continued)
Pin Name
Pin No.
Pin
Type
Pin Description



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