M25P05-AVMP6P datasheet(33/52 Pages) NUMONYX

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M25P05-A

Instructions

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6.12

Release from deep power-down and read electronic

signature (RES)

To take the device out of deep power-down mode, the release from deep power-down and

read electronic signature (RES) instruction must be issued. No other instruction must be

issued while the device is in deep power-down mode.

The instruction can also be used to read, on Serial Data output (Q), the 8-bit electronic

signature, whose value for the M25P05-A is 05h.

Except while an erase, program or write status register cycle is in progress, the release from

deep power-down and read electronic signature (RES) instruction always provides access

to the 8-bit electronic signature of the device, and can be applied even if the deep power-

down mode has not been entered.

Any release from deep power-down and read electronic signature (RES) instruction while an

erase, program or write status register cycle is in progress, is not decoded, and has no

effect on the cycle that is in progress.

The device is first selected by driving Chip Select (S) Low. The instruction code is followed

by 3 dummy bytes, each bit being latched-in on Serial Data input (D) during the rising edge

of Serial Clock (C). Then, the 8-bit electronic signature, stored in the memory, is shifted out

on Serial Data output (Q), each bit being shifted out during the falling edge of Serial Clock

(C).

The instruction sequence is shown in Figure 18.

The release from deep power-down and read electronic signature (RES) instruction is

terminated by driving Chip Select (S) High after the electronic signature has been read at

least once. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is

driven Low, cause the electronic signature to be output repeatedly.

When Chip Select (S) is driven High, the device is put in the standby power mode. If the

device was not previously in the deep power-down mode, the transition to the standby power

mode is immediate. If the device was previously in the deep power-down mode, though, the

transition to the standby power mode is delayed by tRES2, and Chip Select (S) must remain

High for at least tRES2(max), as specified in Table 15. Once in the standby power mode, the

device waits to be selected, so that it can receive, decode and execute instructions.

Driving Chip Select (S) High after the 8-bit instruction byte has been received by the device,

but before the whole of the 8-bit electronic signature has been transmitted for the first time

(as shown in Figure 19), still ensures that the device is put into standby power mode. If the

device was not previously in the deep power-down mode, the transition to the standby power

mode is immediate. If the device was previously in the deep power-down mode, though, the

transition to the standby power mode is delayed by tRES1, and Chip Select (S) must remain

High for at least tRES1(max), as specified in Table 15. Once in the standby power mode, the

device waits to be selected, so that it can receive, decode and execute instructions.

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