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M25P05-AVMP6P 数据表(PDF) 36 Page - Numonyx B.V

部件名 M25P05-AVMP6P
功能描述  512 Kbit, serial Flash memory, 50 MHz SPI bus interface
PDF  52 Pages
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制造商  NUMONYX [Numonyx B.V]
网页  http://www.numonyx.com
标志 NUMONYX - Numonyx B.V

M25P05-AVMP6P 数据表(HTML) 36 Page - Numonyx B.V

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Initial delivery state
M25P05-A
36/52
Figure 20.
Power-up timing
8
Initial delivery state
The device is delivered with the memory array erased: all bits are set to ‘1’ (each byte
contains FFh). The status register contains 00h (all status register bits are 0).
Table 8.
Power-up timing and VWI threshold
Symbol
Parameter
Min
Max
Unit
tVSL
(1)
1.
These parameters are characterized only.
VCC(min) to S low
10
µs
tPUW
(1)
Time delay to Write instruction
1
10
ms
VWI
(1)
Write inhibit voltage
1
2
V
VCC
AI04009C
VCC(min)
VWI
Reset state
of the
device
Chip selection not allowed
Program, erase and write commands are rejected by the device
tVSL
tPUW
time
Read access allowed
Device fully
accessible
VCC(max)



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