DS-AT25DF512C-030 Rev.H

Page 10

2024-01-08

© 2024 Renesas Electronics

AT25DF512C Datasheet

5.

Device Operation

The AT25DF512C is controlled by a set of commands that are sent from a host controller, commonly referred to as

the SPI Master. The SPI Master communicates with the AT25DF512C through the SPI bus, which consists of four

signal lines: Chip Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO).

The SPI protocol defines four modes of operation (0, 1, 2, or 3), with each mode differing in respect to the SCK

polarity and phase, as well as how the polarity and phase control the flow of data on the SPI bus. The

AT25DF512C supports the two most common modes, SPI Modes 0 and 3. The only difference between SPI

Modes 0 and 3 is the polarity of the SCK signal when in the inactive state (when the SPI Master is in standby

mode and not transferring any data). With SPI Modes 0 and 3, data is latched in on the rising edge of SCK and

output on the falling edge of SCK.

Figure 6. SPI Mode 0 and 3

5.1

Dual Output Read

The AT25DF512C features a Dual-Output Read mode that allow two bits of data to be clocked out of the device

every clock cycle to improve throughput. To do this, both the SI and SO pins are used as outputs for the transfer of

data bytes. With the Dual-Output Read Array command, the SI pin becomes an output along with the SO pin.

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