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AT25DF512C 数据表(PDF) 13 Page - Renesas Technology Corp |
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AT25DF512C 数据表(HTML) 13 Page - Renesas Technology Corp |
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13 / 47 page ![]() DS-AT25DF512C-030 Rev.H Page 13 2024-01-08 © 2024 Renesas Electronics AT25DF512C Datasheet 7.2 Dual-Output Read Array The Dual-Output Read Array command is similar to the standard Read Array command and can be used to sequentially read a continuous stream of data from the device by providing the clock signal once the initial starting address has been specified. Unlike the standard Read Array command, however, the Dual-Output Read Array command allows two bits of data to be clocked out of the device on every clock cycle, rather than just one. The Dual-Output Read Array command can be used at any clock frequency, up to the maximum specified by fRDDO. To perform the Dual-Output Read Array operation, the CS pin must first be asserted, and then the opcode 3Bh must be clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the location of the first byte to read within the memory array. Following the three address bytes, a single dummy byte must also be clocked into the device. After the three address bytes and the dummy byte have been clocked in, additional clock cycles result in data being output on both the SO and SIO pins. The data is always output with the MSB of a byte first, and the MSB is always output on the SO pin. During the first clock cycle, bit seven of the first data byte is output on the SO pin, while bit six of the same data byte is output on the SIO pin. During the next clock cycle, bits five and four of the first data byte are output on the SO and SIO pins, respectively. The sequence continues with each byte of data being output after every four clock cycles. When the last byte (00FFFFh) of the memory array has been read, the device continues reading from the beginning of the array (000000h). No delays are incurred when wrapping around from the end of the array to the beginning of the array. Deasserting the CS pin stops the read operation and puts the SO and SI pins into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. Figure 9. Dual-Output Read Array |
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