March 2003

13

MICRF002/RF022

MICRF002/RF022

Micrel

CAGC Pin

VDDBB

VSSBB

675µA

67.5µA

Compa-

rator

1.5µA

15µA

Timout

CAGC

Figure 3. CAGC Pin

Figure 3 illustrates the CAGC pin interface circuit. The AGC

control voltage is developed as an integrated current into a

capacitor C

the decay current is a 1/10th scaling of this, nominally 1.5

µA,

making the attack/decay time constant ratio a fixed 10:1.

Signal gain of the RF/IF strip inside the IC diminishes as the

voltage at CAGC decreases. Modification of the attack/decay

ratio is possible by adding resistance from the CAGC pin to

either V

Both the push and pull current sources are disabled during

shutdown, which maintains the voltage across C

improves recovery time in duty-cycled applications. To fur-

ther improve duty-cycle recovery, both push and pull currents

are increased by 45 times for approximately 10ms after

release of the SHUT pin. This allows rapid recovery of any

voltage droop on C

DO and WAKEB Pins

VDDBB

VSSBB

Compa-

rator

10µA

10µA

DO

Figure 4. DO and WAKEB Pins

The output stage for DO (digital output) and WAKEB (wakeup

output) is shown in Figure 4. The output is a 10

µA push and

10

µA pull switched-current stage. This output stage is ca-

pable of driving CMOS loads. An external buffer-driver is

recommended for driving high-capacitance loads.

REFOSC Pin

250

Ω

200k

Active

Bias

REFOSC

30pF

30pF

30µA

VDDBB

VSSBB

VSSBB

Figure 5. REFOSC Pin

The REFOSC input circuit is shown in Figure 5. Input imped-

ance is high (200k

Ω). This is a Colpitts oscillator with internal

30pF capacitors. This input is intended to work with standard

ceramic resonators connected from this pin to the VSSBB

pin, although a crystal may be used when greater frequency

accuracy is required. The nominal dc bias voltage on this pin

is 1.4V.

SEL0, SEL1, SWEN, and SHUT Pins

to Internal

Circuits

VDDBB

VSSBB

SEL0,

SEL1,

SWEN

Q2

Q3

Q1

VSSBB

SHUT

Q4

Figure 6a. SEL0, SEL1, SWEN

to Internal

Circuits

VDDBB

VSSBB

SHUT

Q2

Q3

Q1

VSSBB

Figure 6b. SHUT

Control input circuitry is shown in Figures 6a and 6b. The

standard input is a logic inverter constructed with minimum

geometry MOSFETs (Q2, Q3). P-channel MOSFET Q1 is a

large channel length device which functions essentially as a

“weak” pullup to VDDBB. Typical pullup current is 5

µA,

leading to an impedance to the VDDBB supply of typically

1M

Ω.