AT45DB321E datasheet(13/80 Pages) RENESAS

13 / 80 page

DS-AT45DB321E-8784 Rev. N

Page 13

9/1/23

AT45DB321E Datasheet

6.2

Continuous Array Read (High Frequency Mode: 1Bh Opcode)

This command can be used to read the main memory array sequentially at the highest possible operating clock

frequency up to the maximum specified by fCAR4. To perform a Continuous Array Read using the standard

DataFlash page size (528 bytes), the CS pin must first be asserted, and then an opcode of 1Bh must be clocked

into the device followed by three address bytes and two dummy bytes. The first 13 bits (PA12 - PA0) of the 23-bit

address sequence specify which page of the main memory array to read and the last 10 bits (BA9 - BA0) of the

23-bit address sequence specify the starting byte address within the page. To perform a Continuous Array Read

using the binary page size (512 bytes), the opcode 1Bh must be clocked into the device followed by three address

bytes (A21 - A0) and two dummy bytes. Following the dummy bytes, additional clock pulses on the SCK pin result

in data being output on the SO (Serial Output) pin.

The CS pin must remain low during the loading of the opcode, the address bytes, the dummy bytes, and the

reading of data. When the end of a page in the main memory is reached during a Continuous Array Read, the

device continues reading at the beginning of the next page with no delays incurred during the page boundary

crossover (the crossover from the end of one page to the beginning of the next page). When the last bit in the

main memory array has been read, the device continues reading back at the beginning of the first page of

memory. As with crossing over page boundaries, no delays are incurred when wrapping around from the end of

the array to the beginning of the array.

A low-to-high transition on the CS pin terminates the read operation and tri-state the output pin (SO). The

maximum SCK frequency allowable for the Continuous Array Read is defined by the fCAR1 specification. The

Continuous Array Read bypasses both data buffers and leaves the contents of the buffers unchanged.

6.3

Continuous Array Read (High Frequency Mode: 0Bh Opcode)

This command can be used to read the main memory array sequentially at higher clock frequencies up to the

maximum specified by fCAR1. To perform a Continuous Array Read using the standard DataFlash page size (528

bytes), the CS pin must first be asserted, and then an opcode of 0Bh must be clocked into the device followed by

three address bytes and one dummy byte. The first 13 bits (PA12 - PA0) of the 23-bit address sequence specify

which page of the main memory array to read and the last 10 bits (BA9 - BA0) of the 23-bit address sequence

specify the starting byte address within the page. To perform a Continuous Array Read using the binary page size

(512 bytes), the opcode 0Bh must be clocked into the device followed by three address bytes (A21 - A0) and one

dummy byte. Following the dummy byte, additional clock pulses on the SCK pin results in data being output on the

SO pin.

The CS pin must remain low during the loading of the opcode, the address bytes, the dummy byte, and the

reading of data. When the end of a page in the main memory is reached during a Continuous Array Read, the

device continues reading at the beginning of the next page with no delays incurred during the page boundary

crossover (the crossover from the end of one page to the beginning of the next page). When the last bit in the

main memory array has been read, the device continues reading back at the beginning of the first page of

memory. As with crossing over page boundaries, no delays are incurred when wrapping around from the end of

the array to the beginning of the array.

A low-to-high transition on the CS pin terminates the read operation and tri-state the output pin (SO). The

maximum SCK frequency allowable for the Continuous Array Read is defined by the fCAR1 specification. The

Continuous Array Read bypasses both data buffers and leaves the contents of the buffers unchanged.

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