APEX20KC datasheet(13/90 Pages) ALTERA

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Altera Corporation

APEX 20KC Programmable Logic Device Data Sheet

The APEX 20KC architecture provides two types of dedicated high-speed

data paths that connect adjacent LEs without using local interconnect

paths: carry chains and cascade chains. A carry chain supports high-speed

arithmetic functions such as counters and adders, while a cascade chain

implements wide-input functions such as equality comparators with

minimum delay. Carry and cascade chains connect LEs 1 through 10 in an

LAB and all LABs in the same MegaLAB structure.

Carry Chain

The carry chain provides a very fast carry-forward function between LEs.

The carry-in signal from a lower-order bit drives forward into the higher-

order bit via the carry chain, and feeds into both the LUT and the next

portion of the carry chain. This feature allows the APEX 20KC architecture

to implement high-speed counters, adders, and comparators of arbitrary

width. Carry chain logic can be created automatically by the Quartus II

Compiler during design processing, or manually by the designer during

design entry. Parameterized functions such as DesignWare functions

from Synopsys and library of parameterized modules (LPM) functions

automatically take advantage of carry chains for the appropriate

functions.

The Quartus II Compiler creates carry chains longer than ten LEs by

automatically linking LABs together. For enhanced fitting, a long carry

chain skips alternate LABs in a MegaLAB structure. A carry chain longer

than one LAB skips either from an even-numbered LAB to the next even-

numbered LAB, or from an odd-numbered LAB to the next odd-

numbered LAB. For example, the last LE of the first LAB in the upper-left

MegaLAB structure carries to the first LE of the third LAB in the

MegaLAB structure.

Figure 6 shows how an n-bit full adder can be implemented in n + 1 LEs

with the carry chain. One portion of the LUT generates the sum of two bits

using the input signals and the carry-in signal; the sum is routed to the

output of the LE. The register can be bypassed for simple adders or used

for accumulator functions. Another portion of the LUT and the carry chain

logic generates the carry-out signal, which is routed directly to the carry-

in signal of the next-higher-order bit. The final carry-out signal is routed

to an LE, where it is driven onto the local, MegaLAB, or FastTrack

interconnect routing structures.

APEX20KC 数据表(PDF) 13 Page - Altera Corporation

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