APEX20KC datasheet(32/90 Pages) ALTERA

32 / 90 page

Altera Corporation

APEX 20KC Programmable Logic Device Data Sheet

Input/Output Clock Mode

The input/output clock mode contains two clocks. One clock controls all

registers for inputs into the ESB: data input, WE, RE, read address, and

write address. The other clock controls the ESB data output registers. The

ESB also supports clock enable and asynchronous clear signals; these

signals also control the reading and writing of registers independently.

Input/output clock mode is commonly used for applications where the

reads and writes occur at the same system frequency, but require different

clock enable signals for the input and output registers. Figure 21 shows

the ESB in input/output clock mode.

Figure 21. ESB in Input/Output Clock Mode

Note (1)

Note to Figure 21:

(1)

All registers can be cleared asynchronously by ESB local interconnect signals, global signals, or the chip-wide reset.

Dedicated Clocks

ENA

data[ ]

rdaddress[ ]

wraddress[ ]

RAM/ROM

128

× 16

256

× 8

512

× 4

1,024

× 2

2,048

× 1

Data In

Read Address

Write Address

Read Enable

Write Enable

Data Out

outclken

inclken

inclock

outclock

ENA

Write

Pulse

Generator

rden

wren

Dedicated Inputs &

Global Signals

To MegaLAB,

FastTrack &

Local

Interconnect

APEX20KC 数据表(PDF) 32 Page - Altera Corporation

APEX20KC 数据表(HTML) 32 Page - Altera Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90

数据表下载