M24M01 datasheet(9/19 Pages) STMICROELECTRONICS

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M24M01

Figure 9. Read Mode Sequences

Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1st and 4th bytes) must be identical.

Read Operations

Read operations are performed independently of

the state of the Write Control (WC) signal.

Random Address Read

A dummy Write is performed to load the address

into the address counter (as shown in Figure 9) but

without sending a Stop condition. Then, the bus

master sends another Start condition, and repeats

the Device Select Code, with the RW bit set to 1.

The device acknowledges this, and outputs the

contents of the addressed byte. The bus master

must

not acknowledge the byte, and terminates

the transfer with a Stop condition.

Current Address Read

The device has an internal address counter which

is incremented each time a byte is read. For the

Current Address Read operation, following a Start

condition, the bus master only sends a Device Se-

lect Code with the RW bit set to 1. The device ac-

knowledges this, and outputs the byte addressed

by the internal address counter. The counter is

then incremented. The bus master terminates the

DEV SEL *

BYTE ADDR

DEV SEL

DATA OUT 1

AI01105C

DATA OUT N

CURRENT

ADDRESS

READ

DEV SEL

DATA OUT

RANDOM

ADDRESS

READ

DEV SEL *

DATA OUT

SEQUENTIAL

CURRENT

READ

DATA OUT N

DEV SEL *

BYTE ADDR

SEQUENTIAL

RANDOM

READ

DEV SEL *

DATA OUT 1

ACK

R/W

NO ACK

ACK

R/W

ACK

R/W

ACK

NO ACK

R/W

NO ACK

ACK

R/W

ACK

R/W

ACK

NO ACK

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