M24M01

2/19

SUMMARY DESCRIPTION

The M24M01 is a 1 Mbit (131,072 x 8) electrically

erasable programmable memory (EEPROM) ac-

Figure 2. Logic Diagram

Table 1. Signal Names

ry protocol. This is a two wire serial interface that

uses a bi-directional data bus and serial clock. The

devices carry a built-in 4-bit Device Type Identifier

tion.

with all memory operations synchronized by the

serial clock. Read and Write operations are initiat-

ed by a Start condition, generated by the bus mas-

ter. The Start condition is followed by a Device

Select Code and RW bit (as described in Table 2),

terminated by an acknowledge bit.

When writing data to the memory, the device in-

following the bus master’s 8-bit transmission.

When data is read by the bus master, the bus

master acknowledges the receipt of the data byte

in the same way. Data transfers are terminated by

a Stop condition after an Ack for Write, and after a

NoAck for Read.

Figure 3. LGA Connections

Note: 1. DU = Don’t Use (should be left unconnected, or tied to

In order to prevent data corruption and inadvertent

Write operations during Power-up, a Power On

Reset (POR) circuit is included. The internal reset

threshold value, and all operations are disabled –

the device will not respond to any command. In the

voltage, below the POR threshold value, all oper-

ations are disabled and the device will not respond

applied before applying any logic signal.

in between. The device ignores all instructions un-

However, the correct operation of the device is not

later of:

These values are specified in Table 9.

E1, E2

Chip Enable

SDA

Serial Data

SCL

Serial Clock

WC

Write Control

Supply Voltage

Ground

AI04048B

SDA

VCC

M24M01

WC

SCL

VSS

2

E1-E2

SDA

VSS

SCL

WC

E1

DU

VCC

E2

AI04051C

M24M01

1

2

3

4

8

7

6

5