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M25P40 数据表(PDF) 27 Page - STMicroelectronics |
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M25P40 数据表(HTML) 27 Page - STMicroelectronics |
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27 / 40 page ![]() 27/40 M25P40 Figure 20. Power-up Timing Table 7. Power-Up Timing and VWI Threshold Note: 1. These parameters are characterized only. INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). Symbol Parameter Min. Max. Unit tVSL1 VCC(min) to S low 10 µs tPUW1 Time delay to Write instruction 1 10 ms VWI1 Write Inhibit Voltage 1 2 V VCC AI04009C VCC(min) VWI Reset State of the Device Chip Selection Not Allowed Program, Erase and Write Commands are Rejected by the Device tVSL tPUW time Read Access allowed Device fully accessible VCC(max) |
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