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VIPER31SP 数据表(PDF) 12 Page - STMicroelectronics |
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VIPER31SP 数据表(HTML) 12 Page - STMicroelectronics |
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12 / 16 page ![]() true for low output current where the output voltage can reach high values, as shown on figure 11 : 20 V can be reached for a nominal regulated one of 14.5 V, with a typical transformer. But a simple clamping zener can limit it to about 17 V with a reasonable dissipated power. The 10 % to 100 % output load regulation is better than +/-7 %. COMPONENTS SIZING The following procedure defines the value of essential parameters for the transformer and the sensing resistance in a typical application. The user can adapt by himself the final design, according to specific needs, if any. - 1. Define the maximum output voltage V MAX OUT for which the converter has still to operate in constant current mode. - 2. Check that the ratio between the minimum operating output voltage V MIN OUT and V MAX OUT is lower than 2.5. This ratio is limited by the overvoltage protection value (Typically 29 V) and VDDreg (Typically 10 V) and their tolerances. - 3. Compute the transformer turn ratio n from primary to secondary with the formula : n = 100 V MAX OUT = np ns - 4. Compute the sense resistance value with the formula : RS = n x 0.175 IOUT - 5. Compute the transformer turn ratio nAUX from auxiliary to secondary with the formula : nAUX = 25 V MAX OUT = na ns - 6. The current control function requires the converter to work in discontinuous mode. The primary inductance value LP of the transformer can be computed by respecting this constraint in all conditions, or by using the following formula : LP = n 10 x V MIN IN x TSW IOUT where : V MIN IN is the minimum input rectified DC voltage from the mains. TSW is the switching period. START UP SEQUENCE An integrated high voltage current source provides a bias current from the DRAIN pin during the start-up phase. This current is partially absorbed by internal control circuits which are placed into a standby mode with reduced consumption and also provided to the external capacitors connected to the VDD and VCC pins. As soon as the voltage on this pin reaches the high voltage threshold VDDon of the UVLO logic, the device turns into active mode and starts switching. The start up current generator is switched off, and the converter should normally provide the needed current on the VDD pin through the auxiliary winding of the transformer, as shown on figure 13. The sum of the external capacitors CSTART on the VDD and VCC pins must be sized according to the time needed by the converter to start up, when the device starts switching. This time tSS depends on many parameters, among which transformer design, output capacitors, capacitor value implemented on the CREF pin (See soft start consideration here after). The following formula can be used for defining the minimum capacitor needed : CSTART > IDD x tSS VDDhyst where : IDD is the consumption current on the VDD pin when switching. Refer to specified IDD1 and IDD2 values. tSS is the start up time of the converter when the device begins to switch. Worst case is generally at full load. VDDhyst is the voltage hysteresis of the UVLO logic. Refer to the minimum specified value. CSTART =CVDD +CVCC is the sum of both capacitors on VDD and VCC pins. Once is defined, allot a standard 4.7 µF / 16 V on the VDD pin, and the rest on the VCC pin. The VDD capacitor insures a correct decoupling of the internal serial regulator between VCC and VDD. Soft start feature is implemented through the CREF capacitor which is also filtering the CREF voltage. The minimum value of this capacitor has to be set according to the switching frequency, in order to filter the charging and discharging current issued from the CREF pin (Refer to the current control description part). It can be increased from VIPer31SP 12/16 |
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